请问hs+pll是否必须使用时钟开关？

在我的应用程序中，我从外部的8 MHz石英，PLL禁用。然后在软件控制下激活PLL，除非现在，它总是工作顺利。关于锁相环的限制，我更喜欢8兆赫石英，而不是任何更快，因为没有必要在输入时钟强制分频器。因此，我在没有成本的情况下具有最大的灵活性。（我的应用程序需要灵活的时钟方案。）



      以下为原文

    In my application, I start with an external 8 MHz quartz, PLL disabled. Then activating the PLL under software control.
Unless now, this always worked smooth. Regarding the PLL limits, I'd prefer an 8 MHz quartz over anything faster as there is no need for a mandatory divider in the input clock. Thus I have maximum flexibility at no cost. (My application calls for a flexible clock scheme.)

是的，我知道这是允许的，但是它是否需要从PLL禁用之后再启用它呢？



      以下为原文

    Right, I know that is allowed, but is it required to start with the PLL disabled and then enable it later?

我甚至没有检查。看看保险丝（CON.）位：由于PLL需要相当多的设置，我不确定它是否被支持。如果被支持，根据我的MCHIP经验，它将工作。如果不是：回到帖子2）：



      以下为原文

    I didn't even check.
Look at the fuse (CONFIG) bits: as the PLL requires quite some settings, I'm not sure whether this is supported.
If it is supported, according to my MChip experience it will work. If not: back to post #2 :)

嗨，答案取决于PIC33。你用的是什么型号？您需要确保引导PLL配置是有效的。也就是说，在为您的设备设置的所有频率限制内。在配置开关中有一个选项（不确定它是否在所有PIC33上）允许芯片在FRC中启动，并在有效时移动到PLL。锁相环可以在没有锁定的情况下对设备进行砖制。这就是为什么有一个故障安全时钟监视器。但是它是如此大量的软件来编写（或者从手册中复制！）要执行开关吗？请看PICREF手册中的7.7.1节。Yorky。



      以下为原文

    Hi,
The answer depends on the PIC33. What type are you using?
You need to ensure that the boot PLL config is valid. That is, within all the frequency limits set for your device.
There is an option in the config switches (not sure if it is on all PIC33s) to allow the chip to start in FRC and move to PLL when valid. The PLL can brick the device if it does not lock. That is why there is a Fail-safe clock monitor.
But is it such a major amount of software to write (or copy from the manual!) to perform the switch?
Have a look at section 7.7.1 in the PIC ref manual.
T Yorky.

除非默认值很好，否则您需要为PLL设置一些自定义设置。无论如何，您必须在运行时指定它们。正如我记得的，他们说在PLL开启的时候不要改变它们。所以，你需要切换PLL关闭，改变设置，然后再次启动PLL。从FRC开始，然后改变为PLL是一步少。另外，当PLL启动时，它会给你一些FRC时间来初始化。



      以下为原文

    Unless defaults are good, you need some custom settings for the PLL. You will have to specify them at run time anyway. As I remember, they say not to change them while PLL is on. So, you will need to switch PLL off, change settings, then start PLL again. Starting with FRC then changing to PLL is one step less. Plus, it gives you some FRC time to do initialization while PLL starts up.

通过在配置字中选择FRC作为初始系统时钟源，然后设置PLL寄存器，然后使PLL作为系统时钟源，在接通电源时最可靠地完成设置主振荡器以使用PLL。使用PLL寄存器的配置字和默认值启用PLL重置电源后，系统FSOC频率为62.5MHz。如果您需要来自主PLL的任何其它FOSC频率，数据表建议您将系统时钟切换到不使用pr的源。在更改任何PLL配置寄存器之前对PLL进行成像。对于您的特定示例，可以动态地将M值（PLLDIV）从0x030更改为0x033，将N2值（PLLPOST）从0x001更改为0x000。这可能起作用，也可能不起作用，因为我不记得在启用PLL之后锁住了PLLDIV寄存器值。这就是我在dsPIC33EP512MU810上使用的代码：



      以下为原文

   
Setting up the primary oscillator to use the PLL is most reliably done at power on by selecting the FRC as the initial system clock source in the configuration words, then set the PLL registers, then enabling the PLL as the system clock source.
 
With a 10.0 MHz external crystal the dsPIC33EP512MU810 system FSOC frequency is 62.5 MHz after power on reset with the PLL enabled using the configuration words and default values for the PLL registers.
 
If you need any other FOSC frequency from the primary PLL the data sheet recommends that you switch the system clock to a source that does not use the primary PLL before changing any of the PLL configuration register.
 
For your specific example it may be possible to change the M value (PLLDIV) from 0x030 to 0x033 and the N2 value (PLLPOST) from 0x001 to 0x000 on the fly. This may or may not work as I do not recall if the PLLDIV register value is locked after the PLL is enabled.
 
This is what the code I have been using on a dsPIC33EP512MU810:/*
 * Define dsPIC33EP512MU810 configuration words
 */
#pragma config GWRP = OFF, GSS = OFF, GSSK = OFF
#pragma config FNOSC = FRC, IESO = OFF
#pragma config POSCMD = HS, OSCIOFNC = OFF, IOL1WAY = OFF, FCKSM = CSECMD
#pragma config WDTPOST = PS32768, WDTPRE = PR128, PLLKEN = ON, WINDIS = OFF, FWDTEN = OFF
#pragma config FPWRT = PWR128, BOREN = OFF, ALTI2C1 = OFF, ALTI2C2 = OFF
#pragma config ICS = PGD1, RSTPRI = PF, JTAGEN = OFF
#pragma config AWRP = OFF, APL = OFF, APLK = OFF
/*
 * Setup the clock to run at 70 MIPS from 10MHz crystal
 */
#define FRC   (7370000L)    /* nominal fast RC frequency */
#define XTL   (10000000L)   /* external 10MHz crystal */
#define FSRC  (XTL)
#define PLL_N1 (2L)         /* PLLPRE  CLKDIV<4:0> range 2 to 33 */
#define PLL_M  (56L)        /* PLLDIV  PLLFBD<8:0> range 2 to 513 */
#define PLL_N2 (2L)         /* PLLPOST CLKDIV<7:6> range 2, 4 or 8 */
#define FOSC (FSRC*PLL_M/(PLL_N1*PLL_N2))
#define FCYC (FOSC/2L)
   
    /*
     * Setup PLL with external crystal
     * This requires that we start using the FRC oscillator.
     * Configure the PLL registers.
     * Then switch to the PLL as the clock source.
     */
   
    /* Test if possible to change clock source */
    if(OSCCONbits.CLKLOCK == 0 )
    {
        register unsigned int CS_Timeout;
   
        /* Select FRC as the CPU clock source */
        __builtin_write_OSCCONH(0b000);
   
        /* request clock switch */
        __builtin_write_OSCCONL(OSCCON | _OSCCON_OSWEN_MASK);
   
        /* wait for oscillator switch to complete */
        for(CS_Timeout=60000; CS_Timeout; --CS_Timeout) if(!OSCCONbits.OSWEN) break;
   
        /* configure PLL register */
        CLKDIVbits.DOZE = 0;
        CLKDIVbits.DOZEN = 0;
        CLKDIVbits.PLLPRE = PLL_N1-2; /* set crystal oscillator prescale */
        #if   PLL_N2==2
          CLKDIVbits.PLLPOST=0; /* N2=2 */
        #elif PLL_N2==4
          CLKDIVbits.PLLPOST=1; /* N2=4 */
        #elif PLL_N2==8
          CLKDIVbits.PLLPOST=3; /* N2=8 */
        #else
          #error invalid PLL_N2 paramenter
        #endif
        PLLFBDbits.PLLDIV = PLL_M-2; /* set PLL multiplier */
   
        /* select primary oscillator with PLL as the CPU clock source */
        __builtin_write_OSCCONH(0b011);
   
        /* request clock switch */
        __builtin_write_OSCCONL(OSCCON | _OSCCON_OSWEN_MASK);
   
        /* wait for oscillator switch to complete */
        for(CS_Timeout=60000; CS_Timeout; --CS_Timeout) if(!OSCCONbits.OSWEN) break;
   
        /* lock in this clock source */
        __builtin_write_OSCCONL(OSCCON | _OSCCON_LOCK_MASK);
    }

是的，我相信时钟交换工作。如果你明白我的意思，那只会让我毛骨悚然。钟是系统的心脏。在CPU继续运行时，实时地使时钟混乱似乎是不明智的，如果可以避免的话。因此，问题是——它是绝对需要的，还是仅仅具有特定的时钟/晶体速度等等。我想我们将玩弄它一旦原型完成，看看事情如何发展。谢谢！



      以下为原文

    Yes, I'm confident clock switching works. It just sort of creeps me out, if you know what I mean. Clocks are the heart of a system. Messing with clocks in real time while the CPU continues to run seems unwise if it can be avoided. Hence the question - whether it's absolutely required, or only with certain clock/crystal speeds, etc.
 
I guess we'll play with it once the prototypes are done and see how things go. Thanks!

如果能够使用默认的PLL设置，则不需要时钟切换。但是，时钟切换没有什么可担心的。系统监视时钟，只有当新时钟准备好时，CPU才切换到新时钟。如果你从FRC开始，你的水晶被破坏了，你就能检测到这一点，然后做点什么。



      以下为原文

    If you can live with default PLL settings, the clock switch is not required.
 
However, there's nothing creepy about clock switches. The system monitors the clock and CPU is switched to the new clock only when (if) the new clock is ready. If you start with FRC and your crystal is broken, you will be able to detect this and then do something about.

我通常将时钟设置为“main”函数中的第一件事，所以在那个时候通常没有其他事情发生。虽然时钟源/速度的改变非常有用，但也有一些很好的情况。如果你确实改变了锁相环设置，你可以测试一下，以确保锁相环在继续工作之前重新锁定。改变时钟没有任何问题。当你没有做很多事情时，这是一个节省电力的好方法，而且系统让你很容易做到这一点。当你控制它发生时，这意味着你也可以控制设备需要同时做什么。因此，诸如定时器、计数器、USB外围设备等需要稳定时钟的问题很容易在过渡期间得到控制。



      以下为原文

    I normally set the clock as one of the first things in the 'main' function so there generally is not much else going on at that time. It tends to be one of those "set and forget" things although there are good cases whene clock source/speed changes are very useful.
Also it you do change the PLL settings, there is a bit you can test to ensure that the PLL is back in lock before you go on.
There is nothing wrong with changing clocks - it is a great way to save power when you are not doing a great deal - and the system lets you do that quite easily. As you control when it happens it means you can also control what else the device is required to do at the same time. Therefore issues such as timers, counters, USB peripherals etc that need a stable clock can easily be controlled over the transition.
Susan

测试…我在另一个论坛上发布帖子有困难。



      以下为原文

    testing... I'm having trouble posting in another forum.