在启用IWDG的情况下进入暂停模式会导致STM8s003F3P6芯片复位

我检查了选项字节，OPT3字节为零，因此WDG_HALT位为0，这意味着当看门狗使能时，MCU应进入暂停模式而不会导致复位。

但是HALT或WFI会产生复位。我在暂停指令之前刷新看门狗计数器，它仍然会产生复位。如果我没有设置IWDG，则不会产生复位，并且程序在中断停止时会正常继续。
我已经为WDG_HALT设置并复位了选项字节，但是当软件启用IWDG并输入暂停时，它总是产生复位。

我该怎么做才能克服这个问题？这是芯片的已知问题吗？


＃STM8S - 停止 - IWDG



以下为原文




I've checked the Option Bytes and the OPT3 byte is zero so the WDG_HALT bit is 0 which means that the MCU should enter Halt Mode without causing a reset when the watchdog is enabled.

However a  HALT or WFI generates a reset. I refresh the watchdog counter prior to the halt instruction and it still generates a reset.  If I do not set up IWDG then no reset is generated and the program continues correctly when it comes out of halt by an interrupt.  
I have set and reset the option byte for WDG_HALT  but it always generates a reset when the IWDG is enabled by software and halt is entered.   

What should I set up to overcome this?  Is this a known problem with the chip?  

  
#stm8s-halt-iwdg