请问有没有办法没有三态没有bidir？

嗨，
我试图用spartan-3AN板命令一个独立的存储器，因为我在Hirose扩展端口上发送数据，信号和地址。
我用ISIM模拟设计，一切都工作得很好，因为我无法模拟内存本身（我有一个模拟模型，但ISIM不能处理1Mb信号）。
我也测试了它，用逻辑分析仪我可以看到信号，地址和写入数据是正确的，时间也很好，但读数不对。
我的猜测是它与双向数据总线有关，我知道内部三态在spartan-3上不再可用，但我无论如何也看不到它的使用而且我不确定是否会重新启动
它可以完成这项工作。
这是三态代码
// tristate.v
// ------------------------------------------------
----
// input =>到FPGA
// output =>到MRAM
// ------------------------------------------------
----
模块三态（
mram_dq_i，
mram_dq_o，
mram_dq_io，
mram_W_o
）;
输入[7：0] mram_dq_o;
输出[7：0] mram_dq_i;
输入mram_W_o;
inout [7：0] mram_dq_io;
wire [7：0] mram_dq_i;
wire mram_W_o;
wire [7：0] mram_dq_io;
wire [7：0] mram_dq_o;
reg [7：0] mram_input_s;
reg [7：0] mram_output_s;
wire mram_W_inv_s;
assign mram_dq_i = mram_input_s;
assign mram_W_inv_s = ~mram_W_o;
分配mram_dq_io =（mram_W_inv_s）？
mram_output_s：{8 {1'bz}};
总是@（*）
开始
mram_input_s
假设存储器正在运行（我试过2确定）并且假设正确的信号和地址是在正确的时间发送的，它只是离开数据总线（dq）和这个内部三态警告。
有没有办法没有三态没有bidir？
谢谢



以下为原文

Hi,

I am trying to command a stand alone memory with a spartan-3AN board, for that I send the data, signals and addresses  on the Hirose expansion port.
I simulate the design with ISIM and everything is working fine as far as i can see for i cannot simulate the memory itself (I have a simulation model but ISIM cannot deal with 1Mb signal).
I tested it too, with a logic analyser i can see that the signals, addresses and writing data are right and that the timing is good too but the reading is not right.

My guess is that it has something to do with the bidirection data bus, I understood that internal tristate are no longer available on spartan-3, but i cannot see anyway not to use it and i am not sure the pull-up which are remplacing it can do the job.

Here is the tristate code

// tristate.v// ----------------------------------------------------//input => to the FPGA//output => to the MRAM// ----------------------------------------------------module tristate(mram_dq_i,mram_dq_o,mram_dq_io,mram_W_o);input[7:0] mram_dq_o;output[7:0] mram_dq_i;input mram_W_o;inout [7:0] mram_dq_io; wire [7:0] mram_dq_i;wire mram_W_o;wire [7:0] mram_dq_io;wire [7:0] mram_dq_o;reg [7:0] mram_input_s;reg [7:0] mram_output_s;wire mram_W_inv_s;assign mram_dq_i = mram_input_s;assign mram_W_inv_s = ~mram_W_o;assign mram_dq_io = (mram_W_inv_s) ? mram_output_s : {8{1'bz}};always@(*)begin  mram_input_s <= mram_dq_io;  mram_output_s <= mram_dq_o;endendmodule
Assuming the memory is functionning (i tried 2 to be sure) and given that the right signals and address is sent at the right timing, it just left the data bus (dq) and this internal tristate warning.

Is there a way not to have bidir without tristate ?

Thanks