为什么我编写代码实现8位计数器会出现这种情况？

如何生成和分发时钟信号“clk”？
它是用BUFG时钟分配缓冲区缓冲的吗？
合成中是否有任何警告或信息消息？
计数器在逻辑模拟中是否正常工作？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

How is the clock signal "clk" generated and distributed?  is it buffered with a BUFG clock distribution buffer?
 
Are there any warnings or info messages from synthesis?
Does the counter function correctly in logic simulation?
 
-- Bob Elkind
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annand写道：
对不起鲍勃，
将信号插入chipcope模块时出错。
我不小心选择了另一个信号而不是所需的“计数”信号。
当我发现错误时，我正要删除帖子。
谢谢你的时间。
阿南德
啊......在ChipScope插入器中找到正确信号的乐趣。
我发现在右边的列中查看表示类型的列很有用
驱动信号的实例。
计数器的输出应来自原语
从“FD”开始而不是“LUT”
我发现的另一件事是默认情况下列表没有按信号名称排序
有助于单击信号名称列标题以在尝试之前对网络进行排序
选一辆公共汽车。
干杯，
的Gabor
-  Gabor



以下为原文

annand wrote:
Sorry Bob,
I made an error while inserting the signal into the chipscope module.  I accidentally chose another signal instead of the required 'count' signal. 
I was about to remove the post as I found out my error. 
Thanks for your time.
 
Anand

Ahh...  the joys of finding the right signals in the ChipScope inserter.
 
I have found that it's useful to look at the column on the right which indicates the type of
instance that drives the signal.  The outputs of a counter should come from primitives
starting with "FD" and not "LUT"
 
Another thing I've found is that the list is not sorted by signal name by default so it
helps to click the signal name column header to get the nets sorted before trying to
select a bus.
 
Cheers,
Gabor
-- Gabor

谢谢，Gabor ...现在，我更喜欢ILA核心的显式实例化而不是'Chipscope Inserter'......这样，你可以确定你在ILA中插入了什么......关心Anand



以下为原文

Thanks, Gabor...
Nowadays, I prefer the explicit instantiation of ILA core instead of 'Chipscope Inserter'... This way, you can be sure what you're inserting into the ILA...

Regards

Anand

annand写道：谢谢，Gabor ......现在，我更喜欢ILA核心的显式实例化，而不是'Chipscope Inserter'...这样，你可以确定你在ILA中插入了什么......关心Anand
当你需要改变你想要监视的信号时，这是一个正确的皇家痛苦。
说真的，要弄清楚要添加到插入核心的信号并不难。
----------------------------是的，我这样做是为了谋生。



以下为原文

annand wrote:
Thanks, Gabor...
Nowadays, I prefer the explicit instantiation of ILA core instead of 'Chipscope Inserter'... This way, you can be sure what you're inserting into the ILA...

Regards

Anand

And it's a right royal pain when you need to change what signals you want to monitor.
Seriously, it's not difficult to figure out what signals you want to add to the inserted core.
----------------------------Yes, I do this for a living.