[问答]

请问有办法在器件的相对两侧的时钟之间进行多路复用吗？

问答对人有帮助，内容完整，我也想知道答案 0 我在找到两个输入时钟之间的多路复用可路由解决方案时遇到了问题。该设计在40MHz范围内的Bank 0上有一个差分时钟，另一个在75MHz范围内的Bank 3上是单端。慢速时钟当前直接进入PLL，但其中一个输出通过原始频率和需要找到它的BUFGMUX方式，以便我可以在它（40MHz）和另一个（75MHz）输入之间进行选择。我在Place＆amp; amp; Route抱怨IOB无法沿时钟路径到达BUFGMUX。在这一点上，我无法找到这个问题的全貌，或者应该采取什么措施来解决它。有没有办法在器件的相对两侧的时钟之间进行多路复用，或者是PLL的输出问题？现在，路径看起来像：慢时钟，Bank 0 - > IBUFGDS - > PLL_BASE - > BUFG - > BUFGMUX 快速时钟，银行3 - > IBUFG -------------------------------------- ^ 目标：xc6slx16 如果我忘记了任何重要信息，请告诉我！以上来自于谷歌翻译以下为原文 I'm having problems finding a routable solution to mux between two input clocks. The design has one differential clock coming in on Bank 0 in the 40MHz range, the other is single ended on Bank 3 in the 75MHz range. The slow clock currently goes straight to a PLL, but one of the outputs passes through the original frequency and needs to find it's way to a BUFGMUX so that I can select between it (40MHz) and the other (75MHz) input. The error I get during Place & Route complains about the IOB not being able to reach the BUFGMUX along a clock path. At this point, I can't find a complete picture of what this issue is, or what should be done to fix it. Is there any way to mux between clocks on opposite sides of the part like this, or is the problem with the output of the PLL? Right now, the path looks like: Slow clock, Bank 0 -> IBUFGDS -> PLL_BASE -> BUFG -> BUFGMUX Fast clock, Bank 3 -> IBUFG --------------------------------------^ Target: xc6slx16 Let me know if I've forgotten any important information! 0
2019-6-25 06:31:06　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答举报李璇相关推荐 • 时钟信号切换可以用多路复用开关吗 2309 • 你真的了解的模拟多路复用器和开关的原理和应用吗？ 3854 • 如何在Mx1051的FlexCAN1中配置简单信号多路复用和扩展信号多路复用？ 391 • 多路复用ICSP引脚如何控制开关？ 2172 • 如何选择多路复用信号链元器件来实现预期性能？ 1120 • 请问如何消除多路复用DAC的输出错误？ 2043 • 如何使用SOT-23薄型多路复用器克服最后时刻的需求变化 940 • 如何通过KC705实现以下时钟多路复用功能吗？ 1442 • 电路和FPGA之间如何设计一个带有ADC的接口以及多路复用 1584 • 低漏电多路复用器在高阻抗PLC系统中的重要性 1671 1个回答

答案对人有帮助，有参考价值 0 与Spartan-6上的BUFGMUX输入的连接非常有限。对于任何给定的BUFGMUX，只有少量（大约4个）时钟输入可以到达MUX - 这些在Sparan-6用户指南UG387图1-3和1-4（及其附近的表格）中有记录。如果你的两个时钟不在同一个BUFGMUX的I0和I1输入端，那么你就不能将它们（直接）复用在一起。 DCM / PLL输出和BUFGMUX输入之间的连接更加稳健，但仍然不完整。器件上半部分的PLL / DCM可以达到32个BUFG的前16个，底部的DCM / PLL可以到达底部的DCM / PLL。时钟输入可以达到哪个PLL以及哪个DCM更加复杂和混乱的限制！所有这些限制都在UG387中详细说明。它们很复杂，因此您需要阅读本节（介于3到17次之间）以确保您理解它们。只有这样你才能弄清楚这个MUX是否可以完成。显然你现在正在做什么（一个是PLL而另一个是直接的）不起作用。也许在另一个上使用DCM，或在两者上使用PLL或...... 祝你好运。 Avrum 以上来自于谷歌翻译以下为原文 The connections to the BUFGMUX inputs on the Spartan-6 are VERY limited. For any given BUFGMUX there are only a small number (around 4) clock capable inputs that can reach the MUX - these are documented in the Sparan-6 User Guide UG387 figures 1-3 and 1-4 (and the tables near them). If your two clocks are not on a pair that can reach the I0 and I1 inputs of the same BUFGMUX then you simply can't mux them together (directly). The connections between the DCM/PLL outputs and the BUFGMUX inputs are more robust, but still not complete. The PLLs/DCMs in the top half of the device can reach the top 16 of 32 BUFGs, and the DCM/PLLs on the bottom can reach the bottom ones. The restrictions on which clock input can reach which PLL and which DCM is even more complex and confusing! All of these restrictions are spelled out in UG387. They are complex so you will need to read this section (somewhere between 3 and 17 times) to make sure you understant them. Only then will you be able to figure out if this MUX can be done. Clearly what you are doing now (a PLL on one and direct for the other) doesn't work. Maybe with a DCM on the other one, or a PLL on both or... Good luck. Avrum

2019-6-25 06:43:04 评论举报陈玉筠