双边计数器无法在Spartan上工作

我正在尝试实现一个verilog代码，用于计算时钟的转换（ei：正向和负向转换）。以下verilog代码使用由“dualedgeregister”模块实现的双边沿寄存器。我使用其中的8个“
dualedgeregister“实现一个8位双边沿寄存器计数器;
8位双边沿寄存器计数器的输出通过模块“main”的输出显示在8个LED上。问题是当我在我的开发板上运行此代码时，只有双边的3个最低有效位
- 寄存器正确存储计数，而计数器的其余5个最高有效位保持随机值或卡在0值;
我可以通过显示8个双边沿寄存器的输出的8个LED来判断双边沿寄存器的每个位的状态。我在Spartan-3E和Spartan-6上尝试了这个代码，结果相同
，即使双寄存器的时钟频率非常慢，也请帮忙！--------------------------------
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--------------- module dualedgeregister（clk，datain，dataout）;
输入clk;
输入数据;
输出数据输出;
reg r1，r2;
总是@（posedge clk）r1总是@（negedge clk）r2指定dataout = clk？
r1：r2;
endmodulemodule main（clkin，leds）;
输入clkin;
输出[7：0] LED;
//寄存器用于减慢输入//时钟信号“clkin”。
reg [26：0] div;
总是@（posedge clkin）div = div + 1;
//我设置//双边沿寄存器将使用的时钟。
电线计数器;
assign counterclk = div [26];
wire [7：0] counterdatain;
wire [7：0] counterdataout;
/ *我生成一个由双边沿寄存器组成的8位计数器，用于计算输入时钟信号clkin的转换次数，无论是正边沿还是负边沿转换。
* / dualedgeregister counter0（counterclk，counterdatain [0]，counterdataout [0]）;
dualedgeregister counter1（counterclk，counterdatain [1]，counterdataout [1]）;
dualedgeregister counter2（counterclk，counterdatain [2]，counterdataout [2]）;
dualedgeregister counter3（counterclk，counterdatain [3]，counterdataout [3]）;
dualedgeregister counter4（counterclk，counterdatain [4]，counterdataout [4]）;
dualedgeregister counter5（counterclk，counterdatain [5]，counterdataout [5]）;
dualedgeregister counter6（counterclk，counterdatain [6]，counterdataout [6]）;
dualedgeregister counter7（counterclk，counterdatain [7]，counterdataout [7]）;
//组合逻辑设置双边沿寄存器输入的下一个//状态。
assign counterdatain = counterdataout + 1;
//双边沿寄存器的输出分配leds = counterdataout;
endmodule



以下为原文

I am trying to implement a verilog code that count the transitions of a clock (ei: both its positive and negative transitions).

The following verilog code use dual-edge-registers implemented by the module "dualedgeregister".
I use 8 of those "dualedgeregister" to implement an 8bit dual-edge-register counter; the output of the 8bits dual-edge-register counter is displayed on 8 leds through the output of the module "main".

The problem is that when I run this code on my devboard, only the 3 least significant bits of the dual-edge-registers are correctly storing the count, while the remaining 5 most significant bits of the counter hold random values or get stuck with a 0 value; I can tell of the state of each bit of the dual-edge-register through the 8 leds which display the output of the 8 dual-edge-registers.

I tried this code on Spartan-3E and Spartan-6 with the same bad result, even when the dual-registers are clocked with a very slow clock.

Please help !


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module dualedgeregister(clk, datain, dataout);
    input clk;
    input datain;
    output dataout;
   
    reg r1, r2;
   
    always @(posedge clk) r1 <= datain;
   
    always @(negedge clk) r2 <= datain;
   
    assign dataout = clk ? r1 : r2;
   
endmodule


module main(clkin, leds);
    input clkin;
    output[7:0] leds;
   
   
    //Register used to slow down the input
    //clock signal "clkin".
    reg[26:0] div;
   
    always @(posedge clkin) div = div + 1;
   
    //I set the clock that will be used by
    //the dual-edge registers.
    wire counterclk;
    assign counterclk = div[26];
   
   
    wire[7:0] counterdatain;
    wire[7:0] counterdataout;
   
    /* I generate an 8bits counter made out of
    dual-edge registers to count the number of transitions
    of the input clock signal clkin whether it be
    a positive-edge or negative-edge transition. */
    dualedgeregister counter0(counterclk, counterdatain[0], counterdataout[0]);
    dualedgeregister counter1(counterclk, counterdatain[1], counterdataout[1]);
    dualedgeregister counter2(counterclk, counterdatain[2], counterdataout[2]);
    dualedgeregister counter3(counterclk, counterdatain[3], counterdataout[3]);
    dualedgeregister counter4(counterclk, counterdatain[4], counterdataout[4]);
    dualedgeregister counter5(counterclk, counterdatain[5], counterdataout[5]);
    dualedgeregister counter6(counterclk, counterdatain[6], counterdataout[6]);
    dualedgeregister counter7(counterclk, counterdatain[7], counterdataout[7]);
   
    //Combinational logic setting the next
    //state of the dual-edge registers inputs.
    assign counterdatain = counterdataout + 1;
   
    //The output of the dual-edge registers
    assign leds = counterdataout;
   
endmodule