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作为一个模拟世界的后裔，我经常可以在走廊上听到些评论，关于数字设计师多么不理解模拟问题。数字设计师们也毫不留情地批评模拟集成电路设计师。这两个阵营泾渭分明，除非参与者们打破界限，一起进入混合信号领域的研究。
对典型的模拟精神，不是所有转换器都用相同的数据格式。一些转换器用无符号二进制数类型，其他转换器使用有符号二进制补码数据。甚至更复杂的问题，转换器输出12位或是14位数据，还有16位输出。还有另一种24位Δ－Σ转换器技术。 
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先不管这些模拟设计结果的目的。对于这些转换器而言，ADC最低有效位的位置是这些8位、16位或是32位字处理器的第0位。对模拟电路设计者来说，这具有重要意义。然而，12位转换器的符号位是处理器的位置11。如果分配16位宽度的变量C为转换器输出值，假定C符号位是位置15。处理器不能从转换器识别出负数，所有来自12位的双极性ADC数据都是正的。因为符号位处于错误位置。
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你可以通过几个步骤来解决这个问题。首先，读－修改－写步骤，将处理器寄存器中的数据移位。CPU读取数据、移动包含数据的寄存器的位到必要的位置，然后将这些数据写回内存。DSP可以在一个时钟周期内完成移位。控制器需要很多时钟周期才能完成移位的过程。如果你选用了这种控制策略，要小心缓存区的不连续性。这意味着缓存区无法辨别DMA控制器是否将新数据写入内存。结果，CPU将缓存区的旧数据进行移位操作。需要记住的是，无论什么时候向左移了一位，就意味着ADC转换结果乘了2。
另一种方式是在处理器循环中将数据右移。这种方式的缺点占用CPU并需要额外指令。另一种选择是直接将转换器与处理器的数据总线相连。如果你将12位转换器的第11位与处理器总线上的第15位相连，那么符号位就会处于正确的位置。然后将数据的第11位到第14位置零来完成数据获取，否则这些位的数据是不确定的。这种方法只适用于有并行接口。在这种方案中，基于DMA移动就不需要数据移位了。 使用串行端口的用户比并行端口的用户要幸运的多，因为大部分处理器的串行端口提供接收的“左移用零填充至最低有效位”或“右移符号位扩展至最高有效位”特点。这种特色大大减少了CPU处理内存中数据的工作。一些串行端口只工作在接收数据长度是2的幂时，例如16位数据长度。这些端口不能工作在12、14或是24位数据长度时。 模拟工程师帮助处理处理器接口问题。据我所知，处理器都是8位、16位或是32位的，我从没听说过12位或14位的处理器。除非所有的模拟芯片设计者突破界限，否则为转换器设计数字接口是理所当然的。阅读ADC数据手册，核对向数字接口传输的位的位置。如果对ADC数据接口做了初始检查，那么你会因为开始的付出获得更多成功。 |
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英文原文：
Analog versus digital: Bridging the ADC-to-processor divide Don’t take things for granted when you are designing the digital interface to a converter. Read the ADC data sheet and verify the bit positions in the transmission across the digital interface. By Bonnie Baker -- EDN, 5/10/2007 As an analog-world descendant, I always hear comments in the hallway about how digital designers don’t really understand analog issues. Digital designers will go so far as to unsympathetically say the same about analog-IC designers. There is no bridge between these two camps unless the participants ride the fence and enter the mixed-signal domain together. True to the analog spirit, not all data converters use the same digital format. Some converters use unsigned-binary-data types; other converters use two’s-complement signed data. To even further complicate matters, some converters produce 12- or 14-bit output words, and others produce 16-bit output words. Yet another technology is the 24-bit delta-sigma converter. Forget the reasons for these analog-design decisions. With all of these converters, the location of the ADC LSB is in the processor’s 0-bit location within the 8-, 16-, or 32-bit word. This situation makes perfect sense to an analog designer. However, the signed-bit of a 12-bit converter resides in position 11 in the processor. If you assign a 16-bit-wide C variable to the converter’s output word, C assumes that the sign bit is in position 15. The processor does not recognize a negative number from the converter and assumes that all codes from the 12-bit, bipolar-in ADC are positive. This situation occurs because the signed bit is in the wrong position. You can approach this problem in several ways. The first, a read-modify-write approach, shifts data in the processor register. The CPU reads the data, shifts the bits in the register containing the data by the necessary amount of bit positions, and writes the data back to memory. A DSP can complete this shift with one cycle. A controller requires many cycles for this shift process. If this strategy is the one you choose, be careful of cache incoherency. Cache incoherency means that the cache is unaware that the DMA controller has placed new words in memory. As a result, the CPU instead shifts the old contents of the cache. It is important to remember that whenever you implement a bit shift to the left, you multiply the ADC results by two. Another option is to shift the data into the right position in a processor loop. On the downside, this approach uses the CPU and requires additional MIPS. Another alternative is to directly connect the converter to the processor’s data bus. If you connect bit 11 of the 12-bit converter to bit 15 of the processor’s data bus, the sign bit will then be in the right place. Complete the data-acquisition task by zeroing register bits 11 through 14. Otherwise, these bits are indeterminate. This approach is possible only with parallel interfaces. In this scenario, the DMA-based transfer need not shift data later on. Serial-port users are more fortunate than parallel-port users because most of the serial ports in processors offer the receiving feature of “left justify and zero fill LSBs” or “right justify and sign-extend MSBs.” This feature significantly reduces the amount of work the CPU must perform once the data is in memory, with one drawback. Some serial ports work only if the received word length is a power of two, such as a 16-bit word length. This receiving feature does not work with 12-, 14-, or 24-bit values. Analog designers can help with the processor-interface problem. All the processors I know about have 8-, 16- or 32-bit data types, but I have never heard of a 12- or 14-bit data type. Until all of the analog-chip designers take the leap and straddle the fence, don’t take things for granted when you are designing the digital interface to a converter. Read the ADC data sheet and verify the bit positions in the transmission across the digital interface. If you do this initial examination of the ADC’s documented digital interface, you will be more successful with your first spin on the design. |
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