请问这个时钟会增加多少噪声？

我想估计当我使用FPGA作为时钟分频器时我会看到多少噪音。
假设我有一个spartan-6（lx25或lx100）在一个不错的PCB上实现，具有足够的去耦电容，符合要求文件（并且每个银行额外增加几个用于良好测量）和一个用于掩埋电容的薄vdd / gnd电介质。
我将在FPGA中运行80 MHz差分时钟（LVDS），并说一半的结构资源以相同的频率运行。
我需要从输入时钟发出一个20 MHz（即4分频）的LVDS时钟。
如果我使用同步分频器在内部产生20 MHz并将其发送到差分LVDS IO，那么这个时钟会增加多少噪声（rms，p-p）？
我最好的情况，典型和最糟糕的假设我不是脑死亡会有所帮助。
此输出时钟将驱动ADC，因此我需要能够表征增加的噪声。
另一种方法是使用外部LVDS时钟缓冲器/分频器IC，因此我试图看看该选项是否值得实施。
谢谢。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

I am trying to estimate whether how much noise I'll see when I use the FPGA as a clock divider. Suppose I have a spartan-6 (lx25 or lx100) implemented on a decent pcb with enough decoupling caps as per the requirements doc (and a couple extra per bank for good measure) and a thin vdd/gnd dielectric for buried capacitance.
I'll be running 80 MHz differential clock (LVDS) into the FPGA and say half of the fabric resources running at the same frequency.
I need to send out an LVDS clock which is 20 MHz (ie divide by 4) from the input clock. If I use a synchronous divider to generate my 20 MHz internally and send it to a differential LVDS IO, how much noise (rms, p-p) would be added to this clock? I best case, typical and worst assuming I am not brain dead would be helpful.
This output clock will drive an ADC so I need to be able to characterize the added noise.

The alternative is to use an external LVDS clock buffer/divider IC so I am trying to see if that option is worth implementing.

Thanks.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.