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我尝试使用下面的Spartan 3通用差分输出缓冲区将单端信号(SClk_P)转换为Diff信号: OBUFDS_SCLK_P:OBUFDS通用映射(IOSTANDARD =>“DEFAULT”)端口映射(O => SClk_P_P, - Diff_p输出(直接连接到顶级端口)OB => SClk_P_N, - Diff_n输出(直接连接到顶级端口) )I => SClk_P); 在实现之后,输入SE信号(SClk_P)是正确的,但是diff输出信号(SClk_P_P或SClk_P_N)是失真的。 附加是SE输入和Diff输出的范围捕获。 顶部迹线是chip_select高电平有效 中间的轨迹是时钟 底部跟踪是数据。 在diff输出捕获上,似乎时钟信号耦合到chip_select跟踪。 可能是这个问题的原因是什么? 该问题与频率无关,单位为KHz或MHz。 谢谢。 Spartan_User 以上来自于谷歌翻译 以下为原文 Hi, I tried to convert my single ended signal (SClk_P) to Diff Signals using Spartan 3 generic differential output buffer below: OBUFDS_SCLK_P : OBUFDS generic map ( IOSTANDARD => "DEFAULT") port map ( O => SClk_P_P, -- Diff_p output (connect directly to top-level port) OB => SClk_P_N, -- Diff_n output (connect directly to top-level port) I => SClk_P ); After implementation, the input SE signal (SClk_P) is correct, but the diff output signal (SClk_P_P or SClk_P_N) is distorted. Attach are scope captures of the SE input and Diff output. The top trace is chip_select active high The middle trace is clock The bottom trace is data. On the diff output capture, it seems the clock signal is coupled to the chip_select trace. What could possibly be the cause of this problem? The issue is independent of frequency either in KHz or MHz. Thank you. Spartan_User |
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示波器轨迹看起来像逻辑分析仪捕获,而不是模拟波形。
建议您生成适当的示波器波形,显示相对于被探测信号的信号幅度,边缘形状和触发电压。 然后让我们看看你有什么。 另外,请描述用于输出的IOSTANDARD和VCCO电源电压。 并且任何终止都应用于信号。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 The scope traces look like logic analyser captures, not analogue waveforms. Suggest you generate proper scope waveforms which show signal amplitude, edge shape, and trigger voltage relative to the signal being probed. Then let's see what you've got. Also, please describe the IOSTANDARD being used for the outputs, and the VCCO supply voltage. And any termination applied to the signals. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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以下是使用模拟示波器捕获的信号,它们显示正确的响应。
这些信号映射到LVDS_25。 IOVCC必须是2.5V,我可以为它们提供3.3V IOVCC吗? 外部没有任何终止。 谢谢。 Spartan_User 以上来自于谷歌翻译 以下为原文 Here are the signals captured with analog scope and they show the right response. These signals are mapped to LVDS_25. Does the IOVCC has to be 2.5V, can I supply them with 3.3V IOVCC? I do not have any termination externally. Thanks. Spartan_User |
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你能描述上面拍摄的范围吗,你说中间的轨迹是CLK,这看起来是否正确它还有问题?如果有尝试再次单端,以确保单个结束的CLK是你所期望的。-J
-------------------------------------------------- -----------------------不要忘记回答,kudo,并接受为解决方案.------------- -------------------------------------------------- ---------- 以上来自于谷歌翻译 以下为原文 Can you describe the scope shot above, you say the middle trace is CLK, this looks correct is there still a problem with it? If there is try making it single ended again to ensure the single Ended CLK is as you are expecting. -J------------------------------------------------------------------------- Don’t forget to reply, kudo, and accept as solution. ------------------------------------------------------------------------- |
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不,这不是问题。
谢谢。 Spartan_User 以上来自于谷歌翻译 以下为原文 No, it's not a problem. Thanks. Spartan_User |
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