代码如下:
input clk;
input [3:0]key;
output reg[7:0]led;
ini
tial led=8'b0;
wire [7:0]signal;
wire finish;
wire finishL2H;
mykey #(4)keyinit(.clk(clk),.key(key),.signal(signal),.finish(finish));
H2L H2Linit(.clk(clk),.rst(1'b1),.signal(finish),.myoutH2L(),.myoutL2H(finishL2H));
always@(posedge clk)
if(finish)
case(signal)
8'b11111110:led[0]<=~led[0];
8'b11111101:led[1]<=~led[1];
8'b11111011:led[2]<=~led[2];
8'b11110111:led[3]<=~led[3];
8'b11101111:led[3]<=~led[4];
8'b11011111:led[3]<=~led[5];
8'b10111111:led[3]<=~led[6];
8'b01111111:led[3]<=~led[7];
default:led<=led;
endcase
endmodule
管脚分配见申请页面
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