怎么使用PWM进行全桥变压器驱动

这是一个HTTP://www. McCHIP.COM/FUMMS/M9597.7.ASPX的副本，但另一个主题有一些额外的链接。



      以下为原文

    This is a duplicate of http://www.microchip.com/forums/m957397.aspx
but the other topic has some extra links.
 

是的，我有问题张贴图像，并尝试了另一个浏览器，但没有喜悦。我不能删除重复的帖子。我可以看到我的草稿中的图片，但当我尝试保存或更新时，会被“拒绝访问”。当我试图插入图像时，我得到了一个默认图标。



      以下为原文

    Yes, I had problems posting the images, and tried another browser, but no joy. I can't delete the duplicate post. I can see the images in my draft, but get "Access denied" when I try to save or update. When I tried to insert image, I got a default icon.
 

最后一个为我工作。



      以下为原文

    That last one works for me.
 

是啊。也许是因为我添加了两张图片。这是另外一个：



      以下为原文

    Yeah. Maybe it was because I added two images. Here is the other one:
 

好的，我将继续这里的讨论，希望复制的线程可以被删除。我刚刚做了另一个模拟，其中相反的MOSFET在25%的占空比下被一起驱动，并且波形看起来不错。有趣的是，输出电压变化不大，变压器初级和次级上的波形仍然是占空比50％的方波。这可能是由于泄漏电感，如L4所示。



      以下为原文

    OK, I'll continue the discussion here, and hopefully the duplicate thread can be deleted. I just did another simulation, where the opposite MOSFETs are driven together at 25% duty cycle, and the waveform seems OK.
 

 
Interestingly, the output voltage has not changed much, and the waveform on the transformer primary and secondary is still a square wave with 50% duty cycle. It may be due to the leakage inductance, shown as L4.
 

我有一个在模拟器中工作的项目，逻辑分析仪在P1和P2上显示PWM信号。然而，虽然我设置了3个周期的延迟时间，但分析器没有显示延迟。这是模拟器I/O的限制，还是我做错了什么？这是我的PWM代码：哈哈！再次拒绝访问！我会试着一次添加几行代码…



      以下为原文

    I have a project working in the simulator and the logic analyzer shows the PWM signals on P1 and P2. However, although I set a delay time of 3 cycles, the analyzer does not show the delay. Is this a limitation pf the simulator I/O, or am I doing something wrong? Here is my code for PWM:
 
HAHA! Access Denied again!!
 
I'll try adding a few lines of code at a time...
 
#define CLKFREQ 16 //Clock Frequency (MHz)
#define PR2_VAL 99 // 199 => 1.25 kHz, 99 => 2.5 kHz
#define PWM1CONSET 0b00000011 // <7>PWM1RSEN (Restart), <6:0> P1DC (Delay Count)
 
/****************************** Setup PWM - Uses TMR2, T2CON **************************/
void SetupPWM(void) {
    INTCONbits.GIE = 0; //Turn off Global Interrupts
// TRISAbits.TRISA5 = 1; // disable output
    PR2 = PR2_VAL; // 16*4*15=960 uSec, 16*4*16=1024 uSec was 199
    CCP1CON = 0b10001100; // <7:6>Half Bridge output P1A, P1B, <5:4>LSB, <3:0> All active high
    CCPR1L = 0; // Pulse width = 40*16=640/960 = 67%
 
    // Duty cycle = (CCPR2L + CCP2CON<4:5>) / 4*(PR4+1)
    // Duty cycle = 10*4 /4*15 = 40/60
    // Period = (PRx+1)*4*Tosc*TMRxPS = 960
    // 16 MHz clock PS=1=>20 kHz PWM, PS=4=>5 kHz PWM
    // 1/20 = (PR+1)*4/16000; PR+1 = 16000/(20*4) = 200; PR = 199
    PIE1bits.CCP1IE = 1;
    PIR1bits.CCP1IF = 0;
    PSTR1CON = 0;
    PSTR1CONbits.STR1B = 1; // 1=CCP1 Output to P1B pin RA2/RA5, 0 = P1B pin is port
    PSTR1CONbits.STR1A = 1; // 1=CCP1 Output to P1A pin RA2/RA5, 0 = P1A pin is port

    PWM1CON = PWM1CONSET;
    TRISCbits.TRISC4 = 0; // enable output RC4
    TRISCbits.TRISC5 = 0; // enable output RC5
    T2CON = T2CONSET; // <6:3> Postscale 1, <0:1> Prescale 1
    T2CONbits.TMR2ON = 1;
    INTCONbits.GIE = 1; //Turn on Global Interrupts
}
 
// P=(PR2+1)*4*TOSC*PS
// PW=NUM*PS*TOSC => NUM=PW*FCLK/PS
// DC=NUM/(4*(PR2+1))
// NUM=DC*(PR2+1)*4
void SetPWM(int DC) { // Duty Cycle DC 0 to 100%
    unsigned long Period; // PWM period in nSec
// unsigned long PulseWidth; // PWM pulse width in nSec
    unsigned long Numerator;
    Period = (1000L*(PR2+1)*4*PSVAL)/CLKFREQ; // 20kHz:50000 nSec = 1000*200*4/16
// PulseWidth = DC * Period / 100; // 50% => 25000 = 50*50000/100
    Numerator = (DC*(PR2+1)*4)/100; // PulseWidth*CLKFREQ/(4*PS);
// Numerator /= 1000;
    CCP1CONbits.DC1B = Numerator & 0b00000011;
    CCPR1L = Numerator >> 2;
}
 

我刚刚有一个关于如何用可变PWM实现推挽拓扑的想法。由于我将使用至少50kHz的变压器驱动器，每个输出在50％占空比的周期将名义上10uSec。使用16 MHz时钟，每个死区时延计数将是1/4＝250毫微秒。因此，20个计数的延迟将产生仅5uSec的导通时间，这相当于半桥模式下两个PWM输出的25%占空比。PIC16F1829有一个32MHz的内部时钟，这对100kHz的PWM很有用。我很惊讶没有PWM模式是真的。具有相同正负驱动的推挽式PWM。但是，我想没有太多的原因，因为减少PWM通过变压器，并进入FWB与电容器滤波器实际上并不改变输出，直到负载足够大，以排水电容器之间的脉冲，然后纹波将非常高。然而，它可能在电容器滤波器之前在DC电路中具有足够的电感。



      以下为原文

    I just had an idea about how to implement a push-pull topology with variable PWM. Since I will be using at least 50 kHz for the transformer drive, the period of each output at 50% duty cycle will be nominally 10 uSec. With a 16 MHz clock, each dead time delay count will be 1/4 = 250 nSec. So a delay of 20 counts would produce an ON time of just 5 uSec, which would be equivalent to 25% duty cycle on both PWM outputs in half-bridge mode.
 
The PIC16F1829 has an internal clock capable of 32 MHz, which would be useful for a 100 kHz PWM.
 
I'm very surprised that there is no PWM mode for true push-pull PWM with equal positive and negative drives. But I suppose there is really not much reason for it, as reduced PWM through a transformer and into a FWB with capacitor filter does not actually change the output until the load is great enough to drain the capacitor between pulses, and then the ripple will be very high. However, it may work with enough inductance in the DC circuit before the capacitor filter.

有没有一个特定的原因，你选择了16F1829的任何16F17XX部分与齿轮？16F1829的主要优点是双MSSP模块。我认为COG外设将完成硬件所需的所有功能。



      以下为原文

    Is there a specific reason you chose the 16F1829 over any of the 16F17XX parts with a COG?  The main advantage of the 16F1829 is the dual MSSP modules.  I think the COG peripheral will do all the functions you need in hardware.  

我看过COG外设，我认为它不会做我想做的，但我真的不熟悉它。我发现这份文件显示了一个“推拉”模式，它似乎是我想要的。但是COG器件只有28和40引脚封装，并且我希望保持20针或更少。这里是模拟器逻辑分析器的屏幕截图，P1A和P1B输出没有死区延迟：http://enginuity..com/pix/electro./MPLABX_SIM_PWM_..pngDared“拒绝访问”。啊！



      以下为原文

    I have looked at the COG peripheral and I didn't think it will do what I want, but I'm really not familiar with it. I found this document that shows a "push-pull" mode that seems to do what I want. But the devices with COG are only in 28 and 40 pin packages, and I want to keep it 20 pins or less. And I don't have any of the devices with COG.
 
BTW, here is the screen shot showing the simulator logic analyzer, and the P1A and P1B outputs having no dead-time delay:
 
http://enginuitysystems.com/pix/electronics/MPLABX_SIM_PWM_delay.png
 
Darned "Access Denied" again. Arrghh!

我看过COG外设，我认为它不会做我想做的，但我真的不熟悉它。我发现这份文件显示了一个“推拉”模式，它似乎是我想要的。但是COG器件只有28和40引脚封装，并且我希望保持20针或更少。这里是模拟器逻辑分析器的屏幕截图，P1A和P1B输出没有死区延迟：http://enginuity..com/pix/electro./MPLABX_SIM_PWM_..pngDared“拒绝访问”。啊！



      以下为原文

    I have looked at the COG peripheral and I didn't think it will do what I want, but I'm really not familiar with it. I found this document that shows a "push-pull" mode that seems to do what I want. But the devices with COG are only in 28 and 40 pin packages, and I want to keep it 20 pins or less. And I don't have any of the devices with COG.
 
BTW, here is the screen shot showing the simulator logic analyzer, and the P1A and P1B outputs having no dead-time delay:
 
http://enginuitysystems.com/pix/electronics/MPLABX_SIM_PWM_delay.png
 
Darned "Access Denied" again. Arrghh!
 

看一看16F1708，16F1709或16F17900的20P部分与齿轮。我认为，您试图完成的大部分功能都是在初始化后很少或根本没有软件干预的情况下构建到COG外设的。



      以下为原文

    Take a look at the 16F1708, 16F1709 or the 16F1769 for 20p parts with a COG.  I think most of the functions you are trying to accomplish are built into the COG peripheral with little or no software intervention after initialization.  

如果我正确理解您的仿真原理图，输出电压应该总是大约VIN／Tr，其中TR是变压器的匝数比（次级匝数除以主匝数，NSEC/NPRI）。这通常被用来制造有时被称为“直流变压器”的东西。它提供高效率的转换，但没有调节输出的能力。如果你想把输出电压调节到一个恒定值，不管输入电压或输出负载电流，那么你将需要和电感器在次级将输出滤波器转变成本质。LY和平均电路（加PWM控制器）。如果您有大师2015或硕士2016会议的演示，请参阅PC1类（电源转换1，由我教）的演示文稿。如果不是，看看这个演示（它类似于主控2015 PC1、http://www-嵌入式DealDealsLab.com /下载/开关%20MOD%20POWER %20%%20% %20i% 2020151105 .ppsx），用于开关转换器工作的一些基本信息。



      以下为原文

    If I understand your simulation schematic correctly, the output voltage should always be approximately Vin/TR where TR is the turns ratio of the transformer (number of secondary turns divided by the primary turns, Nsec/Npri).  This is commonly done to make what is sometimes called a "dc transformer".  It offers conversion at high efficiency but without the ability to regulate the output.
 
If you want to regulate the output voltage to a constant value regardless of input voltage or output load current, then you will need and inductor in the secondary to turn the output filter into what is essentially and averaging circuit (plus a PWM controller).  If you have the presentations for the MASTERS 2015 or MASTERS 2016 conference see the presentations for class PC1 (Power Conversion 1, taught by me).  If not, take a look at this presentation (which is similar to the MASTERS 2015 PC1, http://www.embeddedpowerlabs.com/Downloads/Switch%20Mode%20Power%20Concepts%20Part%20I%2020151105.ppsx) for some basic info on how switching converters work.

12F1501具有4个PWMS，CWG具有死区时间，2个CLC逻辑单元，并且只有8个引脚。这就足够了。



      以下为原文

    12F1501 has 4 PWMs, CWG with dead-time, 2 CLC logic cells, and only 8 pins. This should be enough.