完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
扫一扫,分享给好友
喜
我正在研究斯巴达3E板。 我的设计包含一个处理器,一个RAM,一个网络和一个连接到双同步FIFO的uart。 实际上,uart仅在50MHz频率下工作,并且由于某些原因,其余的设计可能需要不同的频率。 这就是为什么我添加了双同步fifo。 当我模拟我的设计时,它工作得很好......我用不同的频率值测试它。但是当实现板上的设计时......即使我对两个系统都使用相同的频率,也没有显示在screan上 和uart .. 我不明白是什么问题? 欢迎您提出所有想法或建议, martur, 以上来自于谷歌翻译 以下为原文 hi, i'm working on spartan 3E board. my design contains one processor, one RAM, a network and an uart connected to a bisynchronous fifo. actually the uart works only with 50MHz frequency, and, for some reasons, the rest of design may need a different frequency. that's why i added the bisynchronous fifo. when i simulated my design, it works perfectly..and i tested it with different values of frequency..but when à implemented the design on the board..nothing is displayed on the screan,even if i use the same frequency for both system and uart.. i don't understand what is the problem?? all your ideas or suggestions are welcome, martur, |
|
相关推荐
5个回答
|
|
你可能想尝试ChipScope来解决这个问题。
世界上所有的模拟都不会 如果测试台不代表对设计的实际刺激,则发现错误。 的ChipScope 也可以实时工作。 所以即使你正在追逐一个可以在P& R后发现的bug 时序仿真,使用ChipScope找到它可能会更快,至少如果你有想法 从哪里开始寻找。 - Gabor - Gabor 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 You might want to try ChipScope for this problem. All the simulation in the world won't find bugs if the test bench doesn't represent the actual stimulation to the design. ChipScope also works in real time. So even if you're chasing a bug that can be found with post P&R timing simulation, it may be faster to find it with ChipScope, at least if you have an idea where to start looking. -- Gabor -- GaborView solution in original post |
|
|
|
正如您所描述的那样,无法解决此问题。
这是一个很大的逻辑球。 要调试您的设计,您必须以小的,可管理的部分测试,验证和更正设计。 一次取一个设计,然后进行调试。 然后继续下一部分。 您将对设计作品有更好的理解,并且您将学会将每个设计与不同类型的问题联系起来。 UART是一种非常简单的设备。 这是一个很好的起点。 这些论坛中有许多线程讨论UARTS并对它们进行调试。 没有理由不能修改UART以适应各种“主时钟”频率和波特率。 了解UART的工作原理后,您将了解如何根据您的目的和需求修改UART。 这有意义吗? - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 There is no way to troubleshoot this problem as you have described it. It's all one big ball of logic. To debug your design, you must test, verify, and correct the design in small, manageable portions. Take one piece of the design at a time, and debug it. Then move on to the next piece. You will build a much better understanding of the design pieces, and you will learn to associate each piece of the design with different types of problems. A UART is a very simple device. This is a good place to start. There are many threads in these forums which discuss UARTS and debugging them. There is no reason a UART cannot be modified to work with a broad range of "master clock" frequencies and baud rates. Once you understand how the UART works, you will understand how to modify the UART for your purposes and needs. Does this make sense? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
谢谢您的回答,
实际上,就像你说的那样..在开始时,我验证了包含CPU,RAM,网络和UART的设计,并且每件事情都完美无缺。 当我添加双同步fifo时问题开始了。 真正的问题,即使使用fifo,每件事情都完美地模拟,但当我试图在板上测试它时,没有任何东西显示在screan ..所以我怎么能调试它? 特别是在模拟工作正常的时候? 以上来自于谷歌翻译 以下为原文 thank you for your answer, actually, a did like you said..at the begining, i validate the design containing the CPU, RAM,Network and UART, and every thing is working perfectly. problems starts when i added the bisynchronous fifo. the real problem that even with the fifo, every thing works perfectly on simulation,but when i tried to test it on the board, nothing is displayed on the screan..so how can i debug it ?? espacially when the simulation is working correctly?? |
|
|
|
逻辑模拟对查找没有帮助
时间问题 信号完整性问题 异步输入问题 组件或组件故障(或损坏) 如果您的设计在模拟中工作,而不是在真实硬件上工作,这些区别可能有助于集中注意力。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 Logic simulation is not helpful for finding
-- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
|
|
|
你可能想尝试ChipScope来解决这个问题。
世界上所有的模拟都不会 如果测试台不代表对设计的实际刺激,则发现错误。 的ChipScope 也可以实时工作。 所以即使你正在追逐一个可以在P& R后发现的bug 时序仿真,使用ChipScope找到它可能会更快,至少如果你有想法 从哪里开始寻找。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 You might want to try ChipScope for this problem. All the simulation in the world won't find bugs if the test bench doesn't represent the actual stimulation to the design. ChipScope also works in real time. So even if you're chasing a bug that can be found with post P&R timing simulation, it may be faster to find it with ChipScope, at least if you have an idea where to start looking. -- Gabor -- Gabor |
|
|
|
只有小组成员才能发言,加入小组>>
2383 浏览 7 评论
2800 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2263 浏览 9 评论
3336 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2430 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
756浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
545浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
366浏览 1评论
1963浏览 0评论
682浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-11-23 09:10 , Processed in 1.147192 second(s), Total 87, Slave 70 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号