如何制作一个可以保持不同长度的可变长度寄存器

不存在可变长度寄存器 - 如果您认为寄存器是硬件中触发器的集合，则无法在不重新配置FPGA的情况下更改已分配的数量。
现在还不完全清楚您的数据包是什么样的，但您可以尝试将数据放入足够大的RAM中以容纳最大的预期消息，或者将FIFO放入足够长的时间以防止溢出。
然后，您可以使用状态机在闲暇时检查数据。
这样的状态机可能（在状态1中）解析报头并找到消息长度，（在状态2中）记录在计数器寄存器中，然后（在状态3中）使用计数器读取适当数量的单词（可能
在检查消息截断时），然后（在状态4中）检查CRC。
您还可以将传入消息的三个部分存储在三种不同类型的内存中。
这实际上取决于您计划接下来的数据。



以下为原文

There's no such thing as a variable length register - if you consider that a register is a collection of flip flops in hardware, you can't change the number you've allocated without reconfiguring the FPGA.
 
It's not completely clear what your data packets look like, but you could try putting the data into a RAM large enough to hold your largest anticipated message, or a FIFO long enough to prevent overrun. Then you can use a state machine to examine the data at your leisure. Such a state machine might (in state 1) parse the header and find the message length, (in state 2) record that in a counter register, and then (in state 3) use the counter to read the appropriate number of words (probably while checking for message truncation), and then (in state 4) check the CRC.
 
You could also store the three parts of the incoming message in three different types of memory. It really depends on what you plan to do with the data next.