在Fast-Strong情况下是否会出现过多的过冲

呃，好吧。
使用4k7下拉端接SSTL信号不会在SI仿真中产生漂亮的波形。
DDR3接口也有类似的问题。
我所看到的是，使下拉更强，可以抑制过冲。
我已经看到了1k，甚至100R的值。
尝试弄清楚值，直到打捞筒在允许的容差范围内。
在原帖中查看解决方案



以下为原文

Ah, well. Terminating a SSTL-signal with a 4k7 pulldown doesn't make nice looking waveforms in a SI-simulation. A DDR3 interface has similar problems.
 
What i've seen is that making the pulldown stronger dampens the overshoots. I've seen values of 1k, and even 100R. Try to fiddle around with the value until the overshots are within the allowed tolerances.
View solution in original post

在Fast-Strong情况下，我得到了太多的过冲，无论模拟是否在慢速弱情况下的设置时间失败（因为非单一形状）。
我不明白你的意思。
建议：
1.a将并联终端添加到0.9V，哪个值范围提供可接受的结果？
标称值为50欧姆。 
要么
1.b添加系列终止，什么范围的值提供可接受的结果？
标称值为50欧姆。
2.使用SSTL18_I
也：
您可以发布电路和模拟图。
这有助于说明您想要描述的问题。
电路板有多长时间痕迹？
你在DRAM设备引脚上监视电路波形吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

I get too much overshoot in Fast-Strong case, whether the simulation fails for Setup times in Slow-Weak case(because of non monolitic shape).
 
I do not understand your meaning.
 
Suggestions:
1.a  Add parallel termination to 0.9V, what range of values provide acceptable results? Nominal value is 50 ohms.
             or
1.b  Add series termination, what range of values provide acceptable results? Nominal value is 50 ohms.
2.  Use SSTL18_I
 
Also:

• You can post the circuit and the simulation plot.  This would help illustrate the problem you wish to describe.
  
• How long are the circuit board traces?
  
• Are you poltting the circuit waveform at DRAM device pin?
  

-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

呃，好吧。
使用4k7下拉端接SSTL信号不会在SI仿真中产生漂亮的波形。
DDR3接口也有类似的问题。
我所看到的是，使下拉更强，可以抑制过冲。
我已经看到了1k，甚至100R的值。
尝试弄清楚值，直到打捞筒在允许的容差范围内。



以下为原文

Ah, well. Terminating a SSTL-signal with a 4k7 pulldown doesn't make nice looking waveforms in a SI-simulation. A DDR3 interface has similar problems.
 
What i've seen is that making the pulldown stronger dampens the overshoots. I've seen values of 1k, and even 100R. Try to fiddle around with the value until the overshots are within the allowed tolerances.

呃，好吧。
使用4k7下拉端接SSTL信号不会在SI仿真中产生漂亮的波形。
DDR3接口也有类似的问题。
下拉R不用于端接目的，它旨在最小化配置完成后电路板上的噪声瞬变，直到存储器控制器完成初始化。
换句话说，它是信号上的下拉，直到存储器控制器逻辑准备好驱动信号。
地址/控制组信号的经典终端是VTT的50欧姆并行终端（在DDR2的情况下为0.9V）。
如果信号是单负载（Spartan-6 MCB设计的要求）且走线很短，则50欧姆串联终端可替代并联终端方案。
在串联终端的情况下，当组合输出驱动器阻抗加上任何附加串联电阻与电路板传输线阻抗匹配时，实现了理想的结果。
IBIS模型非常清楚输出驱动器阻抗可能会有很大差异。
目标是在过程，温度和电压的变化范围内获得可接受的结果。
“可接受”结果的阈值因设计工程师而异，因此没有完美的解决方案。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Ah, well. Terminating a SSTL-signal with a 4k7 pulldown doesn't make nice looking waveforms in a SI-simulation. A DDR3 interface has similar problems.
 
The pulldown R is not intended for termination purposes, it is intended to minimise noisy transients on the circuit board after configuration is complete until the memory controller is done initialising.  In other words, it's a pulldown on the signal until the memory controller logic is ready to drive the signal.
 
Classic termination on the address/control group signals is a 50-ohm parallel termination to VTT (0.9V in the case of DDR2).  If the signals are single load (a requirement with Spartan-6 MCB designs) and traces are short, a 50-ohm series termination is a substitute for the parallel termination scheme.
 
In the case of series termination, ideal results are realised when the combined output driver impedance plus any additional series resistance matches the circuit board transmission line impedance.  The IBIS models make it quite clear that the output driver impedance can vary quite a bit.  The goal is to achieve acceptable results across variations in process, temperature, and voltage.  The threshold for 'acceptable' results varies from one design engineer to the next, there is no perfect solution.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.