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我想做这样的事情: for(i = 0; i 您可以忽略那里的所有复杂数学,我只需要根据输入参数创建可变数量的寄存器库。 每个寄存器库的大小不同。 我不知道如何跟踪for循环创建的每个寄存器。 我如何处理各种“总和”? 另外,如果我创建一个比我需要的更大的寄存器组并且不分配或访问某些寄存器,那么verilog会减少未使用的寄存器吗? 谢谢 以上来自于谷歌翻译 以下为原文 Hello, I want to do something like this: for (i=0; i<=log2(Nx/2); i=i+1) begin : Gen_Register_BlocksYou can ignore all the complex math there, I just need to create a variable number of register banks based on an input parameter. Each register bank is a different size. I do not know how to keep track of each register created by the for loop. How would I address the various "sum"s? Also, if I create a much larger register bank than I need and do not assign or access certain registers, will verilog reduce the unused registers? Thanks |
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寄存器不是由声明创建的,如:
reg [255:0] my_reg; 或像一堆寄存器 reg [255:0] my_array [31:0] 这些简单的声明my_reg是256位值,它可以在第一种情况下的always块中使用,在第二种情况下它可以在256x32的数组中使用,并且可以在always块中使用。 为了创建一个寄存器,你需要编写将合成它的逻辑: 永远@(posedge clk) 开始 如果(rst) my_reg 恕我直言,循环通常是错误编码,除非用于多个实例化或简化多位操作。 永远记住,您是设计硬件而不是软件,您编写的所有内容都需要转换为硬件逻辑。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Registers are not created by the declaration like: reg [255:0] my_reg; or an array of registers like reg [255:0] my_array [31:0] These simple declare that the my_reg is a 256 bit value and it can be used in always blocks in the first case and in the second that it is array that is 256x32 and can be used in always blocks. In order to create a register you need to write logic that will synthesis to it: always @ (posedge clk)begin if (rst) my_reg <= 256'h0; else my_reg <= my_data;endalways @ (posedge clk)begin my_array[my_addr] <= my_data;end IMHO, Loops are generally bad coding unless used for multiple instantiations or to simplify multiple-bit operations. Always remember that you are design hardware and not software and everything that you write needs to be translated to hardware logic. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.comView solution in original post |
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寄存器不是由声明创建的,如:
reg [255:0] my_reg; 或像一堆寄存器 reg [255:0] my_array [31:0] 这些简单的声明my_reg是256位值,它可以在第一种情况下的always块中使用,在第二种情况下它可以在256x32的数组中使用,并且可以在always块中使用。 为了创建一个寄存器,你需要编写将合成它的逻辑: 永远@(posedge clk) 开始 如果(rst) my_reg 恕我直言,循环通常是错误编码,除非用于多个实例化或简化多位操作。 永远记住,您是设计硬件而不是软件,您编写的所有内容都需要转换为硬件逻辑。 ------您是否尝试在Google中输入问题? 如果没有,你应该在发布之前。太多结果? 尝试添加网站:www.xilinx.com 以上来自于谷歌翻译 以下为原文 Registers are not created by the declaration like: reg [255:0] my_reg; or an array of registers like reg [255:0] my_array [31:0] These simple declare that the my_reg is a 256 bit value and it can be used in always blocks in the first case and in the second that it is array that is 256x32 and can be used in always blocks. In order to create a register you need to write logic that will synthesis to it: always @ (posedge clk)begin if (rst) my_reg <= 256'h0; else my_reg <= my_data;endalways @ (posedge clk)begin my_array[my_addr] <= my_data;end IMHO, Loops are generally bad coding unless used for multiple instantiations or to simplify multiple-bit operations. Always remember that you are design hardware and not software and everything that you write needs to be translated to hardware logic. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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