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我有一个 我的新FPGA设计存在问题。 经过很长一段时间使用我的公司Spartan 2 在BGA csg484封装上迁移到SPARTAN 3A 3400 DSP。 我们有很多 焊接这个CSG484封装和整个电路板的问题已经解决 2次。 第一次球没有完全熔化并且没有完全焊接 由于温度曲线不好，FPGA连接到PCB。 相同的PCB和 相同的FPGA已经用正确的温度曲线再次烘烤 并且球被正确熔化，菊花链被识别并且FPGA被识别 可以编程。 自从 一开始我们在FPGA和其他板载之间的通信方面遇到了问题 芯片。 这似乎是时钟偏差的问题。 但是当里面的资源 对FPGA进行了修改，增加了一个chipcope IPcore来调试，增加了用量 从18％到23％，神奇地认为FPGA的行为更好。 我一直都是 小心检查时间报告，到 了解是否识别了某些设置或保持时间违规，但有 完全没有错误。 我们有3个 每个人都经过相同的双重烘烤程序，并且使用 相同的固件，加载在3个不同的板，行为是完全的 不同。 我曾是 想知道： 1_FPGA 2 烘焙的时间已经消失，我们必须改变它们，因为内部逻辑可以 损坏造成这种随机行为 2_maybe 一些球没有正确焊接，造成巨大的地面反弹 3_我的 机器我安装了从9.2到12.3的所有ISE版本。 我需要他们工作 与旧项目。 是否有可能安装了太多的ISE，但没有使用 同时，可以相互冲突吗？ 任何人都可以 给我一些建议？ 非常感谢 埃马努埃莱 P.S。： FPGA具有80MHz的时钟速度，我猜这对于SPARTAN 3a来说不是问题 DSP。 此外，如果我更改ISE属性（合成，映射和位置和 路由）优化AREA或SPEED的设计，FPGA的行为是 不同，即使定时报告没有错误，无论如何。 以上来自于谷歌翻译 以下为原文 Good day, I have aproblem with my new FPGA design. After a long time using Spartan 2 my companymigrated to SPARTAN 3A 3400 DSP on a BGA csg484 package. We had a lot ofproblems soldering this CSG484 packages and the whole board has been baked2 times. The first time the balls were not melted totally and didn’t solder completelythe FPGAs to the the PCB, due to a bad temperature profile. The same PCBs andthe same FPGAs has been baked another time with the correct temperature profileand the balls were melted properly, the daisy chain was recognized and the FPGAwere possible to be programmed. Since thebeginning we had problems in the communication between FPGAs and other onboardchips. This seemed a problem of clock skew. But when the resources inside theFPGA were modified, adding a chipscope IPcore to debug, increasing the usagefrom 18% to 23%, magically the behaviour of the FPGA was better. I was alwayscareful to check the timing report, tounderstand if some setup or hold time violation were recognized, but there wereno errors at all. We have 3boards, every one was subjected to the same double baking procedure, and withthe same firmware, loaded in the 3 different boards, the behaviour is totallydifferent. I waswondering about: 1_FPGA 2times baked are gone and we must change them ‘cos the internal logic can bedamaged creating this random behaviour 2_maybesome balls are not correctly soldered, creating a huge ground bounce 3_On mymachine I have installed all the ISE version from 9.2 to 12.3. I need them to workwith old projects. Is it possible that too many ISE installed, but not used atthe same time, can conflict with each other? Can anybodygive me some advices? Thanks a lot Emanuele P.S.: theFPGA has a clock speed of 80MHz which I guess is not a problem for a SPARTAN 3aDSP. Also if I change the ISE properties (synthetise, mapping and place androute) to optimize the design for AREA or SPEED, the behaviour of the FPGA isdifferent, even if the timing report is without error, in any case. 
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埃马努埃莱，
1.对所有组装的板进行X射线检查。 这就是你如何判断凸点是否没有正确焊接的方法。 在你浪费你的时间和金钱之前这样做。 你首先必须得到正确的硬件！ 2.我不相信在一台机器上安装所有这些版本是件好事：我在一些地方读过，管理这样一台机器是个问题。 旧版本和较新版本可能会相互冲突。 我以前做的是每当我们开始新的电路板时，设计师就会得到新的电脑。 毕竟，PC是便宜的，而旧的支持旧设计是非常便宜的保险。 我还将每一代新产品冻结成ISE版本，并且不要改变它，直到下一代产品。 我永远不会在一个版本中允许一些设计，而在另一个版本中允许一些设计在我的设计团队中发生！ （只是好的项目控制实践） 3.添加（或删除ChipScope）时的不良行为表明您具有未构造的路径，路径受限，约束错误等等。 检查详细报告：你是否正在考虑你的意图？ 什么是不受约束的？ 它会破坏设计吗？ 约束被忽略了，因为它们发生冲突？ 如果你需要一个参考课程，请阅读我关于时间限制的五篇文章的博客文章。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 Emanuele, 1. Go have all assembled boards X-ray inspected. This is how you can tell if bumps are not soldered properly. Do this before you waste any more of your time and money. You first have to get the hardware right! 2. I do not believe having all those versions on one machine is a good thing: I have read in a few places that managing such a machine is a problem. Older versions, and newer versions may collide with one another. What I used to do is whenever we started a new board, the designers got new PC's. After all, PC's are cheap, and having the old ones to support old designs was very cheap insurance. I also froze each new generation of product toi a version of ISE, and DID NOT CHANGE IT, until the next generation of product. I never, ever, allowed some designs in one version, and some in another version, to happen in my design teams! (Just good project control practices) 3. Bad behavior when you add (or delete ChipScope) is an indication that you have unconstrined paths, poorly constrainted paths, wrong constraints, and so on. Examine the detailed reports: are you constrining what you intended to? What is unconstrained? Will it breeak the design? Are constraints being ignored, because they conflict? Read my blog post of the five articles on timing constraints, if you need a referesher course. Austin Lesea Principal Engineer Xilinx San Jose |
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正如Austin所指出的那样，当设计行为不同时，代码或板与板的变化很小，问题通常是设计不正确。
1）在时序报告文件中报告了多少条路径不受约束？ 2）您的I / O接口是否有OFFSET限制，以确保满足输入建立/保持和输出时钟到输出时序？ ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 As Austin pointed out, when a design behaves differently with small changes to code or from board to board the problem is usually an incorrectly constrained design. 1) How many paths were reported as unconstrained in the timing report file? 2) Did you OFFSET constraints on your I/O interfaces to ensure that input setup/hold and output clock-to-out timing is met? ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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不，我不使用OFFSET约束，不受约束的轨道数为3：
================================================== ============================== 时序约束：在分析时钟“clk_120”之前无约束OFFSET ================================================== ============================== 时序约束：对时钟“clk_120”的分析后无约束OFFSET OUT ================================================== ============================== 时序约束：网络“XSYNC_COUNT_BUFGP”的无约束PERIOD分析 其中clk_120是我的80MHz时钟线的名称，而XSYNC_COUNT_BUFGP只是一个时钟信号，用于具有事件速率（一个非常小的逻辑来完成这项任务） 我不知道如何解释这些信息，但我将开始阅读约束用户指南（对于OFFSET）和奥斯汀的博客。 我希望明天晚上之后我会有更好的结果，或者至少是我现在更清晰的想法。 以上来自于谷歌翻译 以下为原文 No I do not use OFFSET constraints and the number of tracks that are unconstrained are 3: ================================================================================ Timing constraint: Unconstrained OFFSET IN BEFORE analysis for clock "clk_120" ================================================================================ Timing constraint: Unconstrained OFFSET OUT AFTER analysis for clock "clk_120" ================================================================================ Timing constraint: Unconstrained PERIOD analysis for net "XSYNC_COUNT_BUFGP" where clk_120 is the name of my 80MHz clock line and XSYNC_COUNT_BUFGP is just a clock signal which is used to have an event rate (a very small logic to make this task)I do not know exactly how to interpret this information but I'll start to read the constraints user guide (for the OFFSET) and the blog of Austin. I hope that after tomorrow evening I have some better result or at least my clearer ideas as now. |
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>不，我不使用OFFSET约束
如果没有这个，你的I / O时间是未指定的，并且可能是你问题的根本原因。 ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 > No I do not use OFFSET constraints Without this your I/O timing is unspecified and is the likely root cause of your problem. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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2019-6-4 07:53:34
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我想知道的事情：如何从这个时间限制的角度处理双向I / O总线？
以上来自于谷歌翻译 以下为原文 Something over which I was wondering: How can I handle a bidirectional I/O bus from this timings constraints point of view? |
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埃马努埃莱，
博客上一篇文章之后的参考文献列出了时序约束手册，该手册解释了所有约束。 是的，对于由第二个DCM进行了偏斜校正的80 MHz外部接口，您应该有单独的约束。 我怀疑这个界面没有被你拥有的东西正确约束。 检查时间报告的详细版本：它会告诉您到底发生了什么。 寻找那些对您的设计至关重要的信号，并查看它们是否已被适当约束。 如果您在报告中找不到它们，则没有适当的约束.... 您已经正确地开始使用（使用尽可能少的简单约束）。 但现在，您必须扩展以覆盖您缺少的路径。 不幸的是，时序收敛通常比原始设计更多。 这与ASIC的设计没有什么不同 - 它是最后一个需要一些努力工作的问题，我们不能为你做。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 Emanuele, The references after the last article on the blog lists the timing constraints manual, which explains all constraints. Yes, you should have separate constraints for the 80 MHz external interface being deskewed by the second DCM. I suspect this interface is not constrained properly by what you have. Examine the verbose version of the timing report: it will tell you exactly what is happening. Look for those signals that are critical to your design, and look to see if they have been properly constrained. If you can't find them in the report, you do not have the proper constraints .... You have begun properly (use as few, and as simple constraints as possible). But now, you have to extend to cover the paths you are missing. Unfortunately, timing closure is often more work than the original design. This is no different in the design of an ASIC -- it is one of the last issues that requires some hard work, that we can not do for you. Austin Lesea Principal Engineer Xilinx San Jose |
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我不是
要求任何人为我做这份工作，我只是向人们提出建议 比我更有经验。 例如，有人可以抱怨DCM 像我的图中的配置是与什么不同的配置 Xilinx建议（时钟引脚选择错误驱使我们使用它 配置），或者有人可以告诉我“你为什么要使用80Mhz 状态机驱动40Mhz总线？ 这是一个优秀的设计师 永远不会做！”。 我不知道。 我只是想知道我缺乏经验。 关于Xilinx 文档和约束UG，一切都很清楚。 这只是一个坏事 完成旧文档的剪切和粘贴。 你不同意吗？ 这是为了10 http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_constraints_timing_strategies.htm 这是为了 是12.3 http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/cgd.pdf 转到页面 25阅读关于OFFSET IN的句子，请找到提到的图像。 行动， 也许他们在ise 10文档中？ 约束的文档 解释约束如何影响实现的结果，但不解释 为什么必须选择一些行动而不是其他行动。 这就是我提出建议的原因 通过VHDL书籍。 我至少有15本完整的书籍来处理VHDL 编程，但没有解释时序约束如何工作。 啊，这个 该死的想法知道这些东西为何以及如何运作...... 作为苏格拉底 说：“我知道我知道 没有” 但我想知道更多。 只是为了 IT，在80MHz时钟设置时序约束并不容易 约束编辑器没有将80Mhz识别为“可约束”时钟 线。 也许是因为它是由40Mhz派生的。 无论如何，问题都在于 40Mhz的公交车还没有80Mhz的公交车。 我会继续玩约束希望 通过做和学习圣诞老人的一些X光护目镜来检查我的学习 FPGA的球。 以上来自于谷歌翻译 以下为原文 I was notasking anybody to do the job for me, I was just asking advices to people thatare more experienced than me. For example, somebody can complain about a DCMconfiguration like the one in my figure is something that is different from whatXilinx suggest (mistakes in clock pin selection drove us to use thisconfiguration), or somebody can tell me “why the hell are you using a 80Mhzstate machine to drive a 40Mhz bus? This is something that a good designernever do!”. I do not know. I am just wondering about my lack of experience. About the Xilinxdocumentation and the constraints UG, it is everything but clear. It is just a baddone cut and paste of old documentation. Don’t you agree? This is for ise 10 http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_constraints_timing_strategies.htm this is forise 12.3 http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_3/cgd.pdf go to page25 read the sentences about OFFSET IN and please find the mentioned images. Ops,maybe they are in the ise 10 documentation? The constraints' documentationexplains how the constraints affect the implemented result, but do not explainwhy some action must be chosen instead of others. This is why I asked for suggestionsover VHDL books. I have at least 15 complete books which deal with VHDLprogramming, but none that explains how timing constraints worked. Ah, thisdamned idea to know why and how the stuff works… As Socratessaid “I know that I knownothing”but I’d like to know something more. Just to beIT, it is not so easy to set timing constraints for the 80MHz clock when theconstraints editor is not recognizing the 80Mhz as a “constraintable” clockline. Maybe because it is derived by the 40Mhz. Anyway the problems are in the40Mhz bus and not yet in the 80Mhz one. I’ll keep play with constraints hopingto learn by doing and asking Santa Claus for some X-ray goggles to check myFPGAs’ balls. |
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我会继续玩约束希望
通过做和学习圣诞老人的一些X光护目镜来检查我的学习 FPGA的球。 跳过圣诞老人。 中等容量的表面安装组件室应具有X射线检查站。 他们可以检查焊球附着在电路板上。 这将花费一些钱，但是你不必忍受你追逐的问题是与设计相关还是与装配相关的不确定性。 - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 I’ll keep play with constraints hopingto learn by doing and asking Santa Claus for some X-ray goggles to check myFPGAs’ balls.Skip Santa. A moderate volume surface mount assembly house should have an x-ray inspection station. They can check the solder ball attach to the board. It will cost some money, but then you don't have to live with the uncertainty whether the problem you are chasing is design-related or assembly-related. - Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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