振荡器的频率稳定性怎么样

晶体振荡器漂移的两个最大组件是老化和温度。
我确信电压也在那里，但是次要的。
两个漂移元件都具有非常低的频率特性。
换句话说，漂移很慢。
如果您正在寻找高频抖动，那么它们的最大因素是（并且它们结合并相互作用）：
振荡器输出上升/下降时间与输入缓冲器逻辑阈值对比系统噪声
系统噪声（GND，VCC）将移动逻辑阈值电压（相对于GND）或移动电路板信号电平。
对于单端信号，系统中的噪声意味着接收器（或输入缓冲器）的切换延迟的瞬时变化。
该延迟被夸大到单端信号波形具有慢边缘的程度。
这不是频率变化，而是时钟边沿抖动。
时钟边沿不仅会移动，时钟脉冲宽度（或占空比）也会受到影响。
对这些问题敏感的系统通常使用差分信令或在时钟传播路径的每个阶段使用反相缓冲器。
差分信号消除了共模噪声和逻辑阈值不对称作为误差分量，并有效地使信号边沿速率加倍。
使用反相缓冲级对于两个时钟相位或多或少均匀地分配逻辑阈值不对称性。
你的DRAM定时肚脐凝视项目是怎么来的？
- 鲍勃埃尔金德
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以下为原文

The two largest components for crystal oscillator drift are aging and temperature.  I'm sure voltage is in there also, but of secondary importance.
 
Both drift components have very low frequency characteristics.  In other words, drift is slow.
 
If you're looking for high-frequency jitter, the largest contributing factor to these are (and they combine and interact):
 
oscillator output rise/fall time vs. input buffer logic threshold vs. system noise
 
System noise (GND, VCC) will move either logic threshold voltages around (with respect to GND) or move board signal levels around.  For a single-ended signal, noise in the system means instantaneous changes in switching delay for receivers (or input buffers).  This delay is exaggerated to the extent that the single-ended signal waveform has slow edges.
 
This isn't a frequency change, it's a clock edge jitter.  Not only do the clock edges move around, the clock pulse width (or duty cycle) is also affected.  A system which is sensitive to such problems will typically use differential signaling or use inverting buffers at every stage of the clock propagation path.
 
Differential signaling eliminates common mode noise and logic threshold asymmetry as error components, and effectively double the signal edge rates.
 
Using inverting buffer stages distributes logic threshold asymmetry more or less evenly for both clock phases.
 
How's your DRAM timing navel gazing project coming along?
 
- Bob Elkind
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>如果振荡器正在运行，则两个连续的正边缘或负边缘之间的时间间隔为10 ns加上或减去1.000e-12 sec。
不，这意味着对于频率稳定性部分，两个连续的正边缘之间的时间间隔是10纳秒+/- 0.5皮秒，对于周期到周期，抖动性能可能更差。
>再次，如果振荡器运行数天和数月，上述时间戳将与10 ns加上或减去1.000e-12秒相同。
不，时间戳日或月后将减去总时间的+/- 0.005％。
超过30天，相当于129.6秒，超过365天这相当于最坏情况下的1576.8秒。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> If the oscillator is running , time interval between two consequtive postive edge or negative edge  is 10 ns plus  or minus 1.000e-12 sec.

No, this means that the time interval between two consecutive postive edges is 10 nanoseconds +/- 0.5 picoseconds for the frequency stabality portion only, the jitter performance is likely much worse for cycle-to-cycle.
 
> Again if the oscillator is running for days and months , would the above time stamp will be same as 10 ns plus  or minus 1.000e-12 sec.
 
No, the time stamp days or months later would be off by +/- 0.005% of the total time.  Over 30 days, this would be equivalent to 129.6 seconds, over 365 days this would be equivalent to 1576.8 seconds in the worst case.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

谢谢
不，这意味着两个连续的积极时间间隔
对于频率稳定性，边缘是10纳秒+/- 0.5飞秒 
仅部分，抖动性能可能更差
周期到周期。
你能提供一些细节吗？
femtoseconds是什么意思？
问候
费萨尔



以下为原文

Thanks
 
No, this means that the time interval between two consecutive postive edges is 10 nanoseconds +/- 0.5 femtoseconds for the frequency stabality portion only, the jitter performance is likely much worse for cycle-to-cycle.
 
could you provide some detail ?
 
What do you meant by  femtoseconds ?
 
Regards
 
Faisal

femtoseconds是什么意思？
我一整天都在等待这个机会！在这里，你去吧！ -  Bob Elkind
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以下为原文

What do you meant by  femtoseconds ?

I've been waiting for this opportunity all day long!

Here ya go!

- Bob Elkind
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不，这意味着对于频率稳定性部分，两个连续的正边缘之间的时间间隔是10纳秒+/- 0.5飞秒，对于周期到周期，抖动性能可能更差。
你能提供一些细节吗？
频率稳定性（或不稳定性）是累积的 - 它描述了长期频率变化。
抖动不是累积的。
由于抖动，长期的净频率变化为零。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

No, this means that the time interval between two consecutive postive edges is 10 nanoseconds +/- 0.5 femtoseconds for the frequency stabality portion only, the jitter performance is likely much worse for cycle-to-cycle.

could you provide some detail ?

Frequency stability (or instability) is cumulative -- it describes long-term frequency changes.
Jitter is not cumulative.  Net frequency change due to jitter, long-term, is zero.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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>飞秒是什么意思？
哎呀，我的单位转换中有一个小错误。
它应该是0.5皮秒或500飞秒。
我编辑了我之前的回复以纠正错误。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> What do you meant by  femtoseconds ?
 
Oops, I had a small mistake in my units conversion.  It should have been 0.5 picoseconds or 500 femtoseconds.
 
I edited my previous reply to correct the mistake.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

它应该是0.5皮秒或500飞秒。
或500,000阿秒。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

It should have been 0.5 picoseconds or 500 femtoseconds.

Or 500,000 attoseconds.
 
- Bob Elkind
SIGNATURE:
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Summary:
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我一整天都在等待这个机会！你走了！
好时机鲍勃。
我正在设计用于长电缆故障查找的数据采集系统。
我已经制作了两块相同的电路板。
每块板都有FPGA，ADC，PSRAM和GPS接收器。
目的是同时开始数据采集，解释如下
计算两个系统之间相对于公共参考脉冲的时间延迟。
例如，两个系统之间的时间延迟是delatt。
我希望每30分钟在系统中开始数据采集
所以第一个系统开始说30分钟，而第二个系统开始30分钟+ delatt。
该过程持续运行数周或数月。
如果两个系统之间的时间偏移或误差为100 ns，我将在10米的故障位置出错。这对中压电缆来说是合理的。
反正有计算时间偏移或误差吗？
问候
费萨尔



以下为原文

I've been waiting for this opportunity all day long!

Here ya go!
 
Good timing Bob.
 
 
I am working on design of  data acquisition system for fault finding in long cables.
 
I have bulid two same boards . Each board  has FPGA, ADC,PSRAM and GPS receiver.
 
Objective is to start the data acquisition at the same time which is explained as follows
 
Caluclate the time delay between two system with respect to a common referrence pulse.
 
For e.g time delay between two system is delatt .
 
I wish to start the data acquisition in both the systema  for every 30 mins
 
So first system starts say at 30 mins ,while second system starts at  30 mins + delatt.
 
 
This process runs continuously for weeks or months.   
 
If  the time offset  or error between two systems is for e.g 100 ns , I will get an error in fault location of 10 meters.Which is reasonable  for Medium voltage cables.
 
Is there anyway to calculate time offset  or error  ?
 
Regards
 
Faisal
 

我正在设计用于长电缆故障查找的数据采集系统。
请描述您要查找的故障类型。
目的是同时开始数据采集，解释如下
什么数据采集？
计算两个系统之间相对于公共参考脉冲的时间延迟。
你的意思是两个系统之间的电缆传播时间？
例如，两个系统之间的时间延迟是delatt。
我希望每30分钟在两个系统中开始数据采集
所以第一个系统开始说30分钟，而第二个系统开始30分钟+ delatt。
什么数据采集？
该过程持续运行数周或数月。
如果两个系统之间的时间偏移或误差为100 ns， 
我会在10米的故障位置得到错误。这是合理的 
适用于中压电缆。
如何计算时间偏移？
（我在讨论中间切换名称或术语感到困惑）或者你的意思是电缆传播时间？
反正有计算时间偏移或误差吗？
最简单的方法是从A发送脉冲到B，B将脉冲返回到A，A测量往返延迟。
B可以为返回的脉冲添加符号，这确认了完整往返的完整性。
这类似于时域反射计（TDR）的作用。
[请注意Xilinx的人员，我是第一个将Xilinx FPGA引入Tektronix的工程师，它是否显示？]
您可以根据需要制作精细或简单的系统，包括信号损伤检查和带宽检查。
每个节点可以发送唯一的ID号，以便可以在每个节点中本地构建“映射”，其总结所有连接，从而可以保留每个链接的记录和历史以供参考和用于错误记录或报告。
真的，天空是迷茫的。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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你读过手册了吗？
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以下为原文

I am working on design of  data acquisition system for fault finding in long cables.

Please describe the fault types you are trying to find.

Objective is to start the data acquisition at the same time which is explained as follows

What data acquisition?

Calculate the time delay between two system with respect to a common reference pulse.

You mean the cable propagation time between two systems?

For e.g time delay between two system is delatt .
I wish to start the data acquisition in both the systems for every 30 mins
So first system starts say at 30 mins, while second system starts at  30 mins + delatt.

What data acquisition?

This process runs continuously for weeks or months.   
If  the time offset  or error between two systems is for e.g 100 ns , I will get an error in fault location of 10 meters.Which is reasonable  for Medium voltage cables.

How is time offset calculated? (I get confused by switching names or terms in mid-discussion)
Or do you mean cable propagation time?

Is there anyway to calculate time offset  or error  ?

Easiest way is to send a pulse from A to B, B returns the pulse to A, A measures round trip delay.  B can add a symbol to the returned pulse which confirms integrity of complete round trip. This is analogous to what a time-domain reflectometer (TDR) does.
 
[note to Xilinx folks, I was the engineer who first brought Xilinx FPGAs into Tektronix, does it show?]
 
You can make this sort of system as elaborate or simple as you like, including signal impairment checking and bandwidth checking.  Each node can transmit a unique ID number, so that a 'map' can be built locally in each node which summarises all connections, and thereby records and history of each link can be retained for reference and for error logging or reporting.  The sky's the lmit, really.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
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短发
[请注意Xilinx的人员，我是第一个将Xilinx FPGA引入Tektronix的工程师，是否会显示？]，
能告诉我你想传达的信息吗？
问候
费萨尔



以下为原文

Bob
 
[note to Xilinx folks, I was the engineer who first brought Xilinx FPGAs into Tektronix, does it show?],
 
Could you please let me know what message you wish to convey ?


Regards


Faisal

TDR的领先制造商之一是泰克公司。
由于我在帖子中提到了TDR（或类似TDR的方法），我想我会毫无理由地提到Tektronix。
在我第一次使用Xilinx 3030 FPGA进行设计时，泰克公司只是一家Altera公司。
那是很多年前的事了，Tektronix当时要大得多，我的头发也要大得多。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

One of the leading manufacturers of TDRs is Tektronix.  Since I referred to TDRs (or a TDR-like approach) in my post, I figured I would toss in a gratuitous reference to Tektronix.  At the time I first designed in a Xilinx 3030 FPGA, Tektronix was an Altera-only company.  That was many years ago, and Tektronix was much much bigger then, and my hair was much bigger.
 
- Bob Elkind
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2. Search the forums (and search the web) for similar topics.
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

你可能在这方面比我更专业，但我认为这些电缆的交流频率非常高。
有没有办法让你使用基本50赫兹（我认为英国）作为这个应用的准确时间基准？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

You are probably much more of an expert in this area than I am, but I thought that the AC frequency of these cables were extremely high precision.  Is there a way for you to use the base 50 Hz (I think for the UK) as your accurate time base for this application?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

你可能比我更像这方面的专家
我只是在学习
但我认为这些电缆的交流频率非常高
频率变化为50 Hz +或 -  2.5 Hz。
如果系统违反，过频或欠频控制继电器将完成其工作。
有没有办法让你使用基本50赫兹（我认为英国）作为这个应用的准确时间基准？
我很害怕，我无法效仿
此外，我使用GPS时间戳进行时基校准。
感谢您的关注
最好的祝福
费萨尔



以下为原文

You are probably much more of an expert in this area than I am
 
 I am just learning
 
but I thought that the AC frequency of these cables were extremely high precision
 
Frequency variation as 50 Hz + or -  2.5 Hz . If the system violates , Over frequency or under frequency controll relay will do its job.
 
Is there a way for you to use the base 50 Hz (I think for the UK) as your accurate time base for this application?
 
I am afraid , I can't follow


Moreover I am using GPS time stamp for time base alignment.


Thanks for your interest 


Best Regards


Faisal

 





 

MCGETT
现在我跟着你。
但我认为这些电缆的交流频率非常高
这些电缆的频率容差为50 Hz +或 -  2.5 Hz。
因此，这将导致两个系统之间的延迟（需要同步）为（1 / 2.5），即4秒。
如果您使用16位分辨率对100个Ms / s的数据进行四个电源周期的采样，则需要具有（16 MB（有用数据）+ 80 MB的RAM（对于正负0.4秒的开销，我会说，不是
有用的数据）。基本上资源使用率要高得多。也不确定50 Hz +或 -  2.5 Hz的稳定性.50 Hz波形（电感或电容）应该有相移，取决于负载
那么如果电缆上的负载是纯电阻的，那么频率稳定性就会保持不变，我希望50 Hz可以用于时间同步。请纠正我，如果我错了
问候
费萨尔



以下为原文

mcgett
 
Now I follow you.
 
but I thought that the AC frequency of these cables were extremely high precision
 
Frequency tolerance in these cables are as  as 50 Hz + or -  2.5 Hz.  So this will cause delay between two system (needs to be synchronised)  as (1/2.5) which is 4 seconds. If  you are sampling  data in 100 Ms/s with 16 bit resolution for  four power cycles , you need to have a RAM of  (16 MB  (useful data)  + 80 MB (for plus or minus 0.4 second overhead , I would say , not a useful data) . Basically resource usage is much higher. Also not sure about this 50 Hz + or -  2.5 Hz. stability .Also there should be a phase shift in the 50 Hz waveform ( either inductive or capcacitive) , depends on the load. So if the load on the cable is purely resistive , frequency stability is maintained indefinitley , I hope  50 Hz can be used for time synchronization. Please correct me , If I am wrong

 
Regards
 
Faisal

mcgett写道：
你可能在这方面比我更专业，但我认为这些电缆的交流频率非常高。
有没有办法让你使用基本50赫兹（我认为英国）作为这个应用的准确时间基准？
虽然是英国居民，但我不是该专题的专家。
但是，我知道瞬时电源频率从50Hz变化到可测量的量，当负载短期增加时变慢。
我记得在几个周期内读到24小时稳定性非常好！
适用于电动clocsk，不适合频率测量。
另见http://www.claverton-energy.com/aspects-of-the-dynamics-of-the-uk-national-grid.html
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

 

mcgett wrote:
You are probably much more of an expert in this area than I am, but I thought that the AC frequency of these cables were extremely high precision.  Is there a way for you to use the base 50 Hz (I think for the UK) as your accurate time base for this application?

 
Although a UK resident, I am not an expert in the topic. However, I do know that the instantaneous mains frequency varies from 50Hz by measurable amounts, getting slower when load increases short term. I remember reading that the 24-hour stability is very good, within a few cycles! Good for electric clocsk, not good for frequency measurements.
 
also see http://www.claverton-energy.com/aspects-of-the-dynamics-of-the-uk-national-grid.html
 
 

------------------------------------------
"If it don't work in simulation, it won't work on the board."

我记得读过这个
在几个周期内24小时稳定性非常好！
好的
电动clocsk，不适合频率测量。
你有两个变电站A和B之间的相移数据（长期）吗？
亲切的问候
费萨尔



以下为原文

 
I remember reading that the 24-hour stability is very good, within a few cycles! Good for electric clocsk, not good for frequency measurements.


Do you have any data  (long term) of  phase shift   between two substations A and B  ?
 
Kind Regards
 
Faisal

 

就像我的帖子上写的“我记得读书”。如果你在英国，为什么不直接联系国家电网？http：//www.nationalgrid.com/corporate/about+us/contact+us/
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

Like my post said "I remember reading".

If you are in the UK, why not contact National Grid directly?
http://www.nationalgrid.com/corporate/about+us/contact+us/
------------------------------------------
"If it don't work in simulation, it won't work on the board."