除了接地之外，还有什么办法可以使引脚工作

费萨尔
引脚（引脚编号和引脚信号名称）是否出现在设计摘要布线后引脚报告中？
您是否有其他具有相同行为的电路板？
如果在设计中将信号置为低电平（作为测试用例），电路板上的引脚是否变为低电平？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Faisal,
 
Does the pin (pin number and pin signal name) appear in the design summary post-route pin report?
Do you have other boards which exhibit the same behaviour?
If you tie signal LOW in your design (as a test case), does the pin go LOW on your board?
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢Bob，
引脚（引脚编号和引脚信号名称）是否出现在设计摘要布线后引脚报告中？
是的。
您是否有其他具有相同行为的电路板？
我有另一个。
它很好，这意味着特定的引脚响应很好。
如果在设计中将信号置为低电平（作为测试用例），电路板上的引脚是否变为低电平？
你的意思是，将那个特定的引脚连接到地面？
。
如果你的答案是肯定的。
我的回答是我没试过。
我有一个备用的FPGA芯片，我会焊接它。
你有什么建议吗？
问候
费萨尔



以下为原文

Thanks Bob,
 
Does the pin (pin number and pin signal name) appear in the design summary post-route pin report?
 
Yes it is.
 
Do you have other boards which exhibit the same behaviour?
 
I have other one. It is fine , which means that particular pin  is responding fine.
 
If you tie signal LOW in your design (as a test case), does the pin go LOW on your board?
 
Do you mean  , to connect that particluar pin to ground  ? . If your answer is yes. My answer  is  I did not try that.
 
I have a spare FPGA chip , I will solder it . Do you have any suggestion ?
 
Regards


Faisal

 
 

如果在设计中将信号置为低电平（作为测试用例），电路板上的引脚是否变为低电平？
你的意思是，将那个特定的引脚连接到地面？
。
如果你的答案是肯定的。
我的回答是我没试过。
不，我的意思是使用引脚作为输出从FPGA驱动引脚LOW。
这将验证FPGA是否可以将引脚驱动为低电平，假设电路板上没有故障将引脚拉高。
我有一个备用的FPGA芯片，我会焊接它。
你有什么建议吗？
在更换FPGA之前，我建议切断这个FPGA引脚的电路板走线。
通过迹线切割，FPGA引脚是否正常工作（可以驱动为低电平）？
如果是这样，故障是在电路板上，而不是在FPGA中 - 这可以帮助您免于更换FPGA。
切割迹线时，尝试找到可以触及示波器探头的迹线两侧的位置，并以易于修复的方式切割迹线。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

If you tie signal LOW in your design (as a test case), does the pin go LOW on your board?
Do you mean  , to connect that particluar pin to ground  ? . If your answer is yes. My answer  is  I did not try that.

No, I meant drive the pin LOW from the FPGA, using the pin as an output.  This would verify that the FPGA can drive the pin LOW, assuming there is no fault on the board which pulls the pin HIGH.

I have a spare FPGA chip , I will solder it . Do you have any suggestion ?

Before replacing the FPGA, I would suggest cutting the circuit board trace to this FPGA pin.  With the trace cut, does the FPGA pin behave correctly (can it drive LOW)?  If so, the fault is on the board, and not in the FPGA -- this saves you from replacing the FPGA.
 
When cutting the trace, try to find a spot where both sides of the trace are accessible for scope probe, and cut the trace in a manner which is easy to repair.

 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢Bob，
如果在设计中将信号置为低电平（作为测试用例），电路板上的引脚是否变为低电平？
首先，我尝试过切换 
其次我尝试过低价。
引脚始终保持高电平
在更换FPGA之前，我建议切割 
电路板跟踪此FPGA引脚。
随着痕迹切割，做了 
FPGA引脚表现正常（可以驱动为低电平）吗？
如果是，则故障开启
电路板，而不是FPGA  - 这可以节省您更换电路板
FPGA。
好点子 。
我应该试试。
我所做的如下
跟踪从FPGA I / O运行到BGA（PS RAM）。
我已经移除了BGA并在那里进行探测（BGA点）。
然后我在FPGA I / O上准确探测它。
理论上两个测试都是一样的。
亲切的问候
费萨尔



以下为原文

Thanks Bob,
 
 
If you tie signal LOW in your design (as a test case), does the pin go LOW on your board?
 
First I have tried with toggling 


Second I have tried with  low.


Pin always  stays always high
 
 
Before replacing the FPGA, I would suggest cutting the circuit board trace to this FPGA pin.  With the trace cut, does the FPGA pin behave correctly (can it drive LOW)?  If so, the fault is on the board, and not in the FPGA -- this saves you from replacing the FPGA.
 
Good point . I should try that. What I have done is as follows

 
Trace runs from FPGA I/O to BGA (PS RAM) . I have removed the BGA and probe it there ( BGA point) .
 
Then I probe it exactly on the FPGA I/O .  Theortically both tests are same.
 
 
Kind Regards
 
Faisal