VHDL新手对寄存器有疑问

digikev写道：
你好，
我是VHDL的新手，但对寄存器有疑问。
我正在研究一些VHDL逻辑，我被告知“无论是谁写了这个，都知道很多关于VHDL，但没有关于FPGA时序”。
下面的寄存器样本。
我被告知它没有“时钟”，并且它是“未经同步的”。
为什么需要时钟？
全球写不是时钟吗？
附：
怜悯新手。
;-)
signal EventStart_REG：std_logic_vector（7 downto 0）;
（“00000000”＆amp; EventStart_REG）当（n_ce2 ='0'和n_sdras ='0'和ea（13 downto 2）= X“033”）否则---------------
---------
-----------------------------------------------活动开始注册
-  ---------------------------------------------
进程（PC1_GlblWr，PortD_Data_bus_sel，PortD_Direction_out_sel，Port_D_Wr，PortD_asAddressBus）开始if（（PC1_GlblWr ='0'）和（PortD_asAddressBus = x“A5”）和（PortD_Data_bus_sel ='1'）和（PortD_Direction_out_sel ='1'））然后EventStart_REG
结束如果;结束过程;
该代码实现了一个锁存器。
在过去的异步总线（如旧的IBM PC-AT总线）中，如果从机与地址匹配，则数据在写选通的上升沿被锁存到从设备。
类似地，从器件将匹配地址并在读取选通脉冲低电平期间适当地驱动数据总线。
当总线由具有8 MHz时钟的处理器驱动时，这非常有效。
但是现在大多数事情都是同步的，原因已经在这里和其他地方讨论过了。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

digikev wrote:
Hello,
I'm new to VHDL, but have a question regarding registers.  I'm looking at some VHDL logic, and I'm told that "whoever wrote this knew plenty about VHDL, but nothing about FPGA timing".  Sample of a register below.  I'm told it has no "clocks", and that it is "unsyncronized".  Why does it need a clock? Wouldn't the Global Write be the clock?
P.s. Have mercy on the newbie. ;-)
 
 
signal EventStart_REG: std_logic_vector (7 downto 0);
 
 ("00000000" & EventStart_REG)  when ( n_ce2 = '0' and n_sdras='0' and ea(13 downto 2)=X"033") else ------------------------
 
---------------------------------------------
--          Event Start Register         --
---------------------------------------------
process(PC1_GlblWr, PortD_Data_bus_sel, PortD_Direction_out_sel, Port_D_Wr, PortD_asAddressBus)
begin
  if ( (PC1_GlblWr='0') and (PortD_asAddressBus=x"A5") and (PortD_Data_bus_sel='1') and (PortD_Direction_out_sel='1') ) then
    EventStart_REG  <= Port_D_Wr;
  end if;
end process;

 
That code implements a latch.
 
Back in the old days of asynchronous buses (like the old IBM PC-AT bus), data were latched into a slave device on the rising edge of the write strobe if the slave matched the address. Similarly, the slave would match the address and drive the data bus appropriately during the assertion of the read strobe low. This worked well enough when buses were driven by processors with an 8 MHz clock.
 
But these days most everything is synchronous for reasons which have been discussed here and elsewhere ad naseum.
----------------------------Yes, I do this for a living.

你在学习VHDL吗？
为什么这段代码对您有用？
如果您对VHDL编码风格的基础知识感兴趣，您可能需要查看ISE（编辑>语言模板）中提供的编码模板。
当有更简单，更通用的例子可供学习时，为什么还要烦恼这段代码呢？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Are you learning VHDL?  Why is this snippet of code of any interest to you?
 
If you are interested in the basics of VHDL coding style, you might want to look at the coding templates which are provided in ISE (EDIT > Language Templates).
 
Why bother with this bit of code when there are simpler and more general examples from which to learn?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我来自“Altera之地”和基于逻辑示意图的逻辑，因此VHDL对我来说是一个新手。
为什么这个代码？
我现在正在寻找一些旧的（公司产品）逻辑，因为他们需要添加一个新功能。
不幸的是，制造这种混乱的人早已不复存在。
我已经确定，任何轻微的改变都会导致新的编译逻辑完全搞砸了相关电路板的现有功能/性能。
你能说时间错误吗？
我相信这个逻辑需要完全重写，所以我正在寻找外部承包商/专业人士来完成这项工作，因为....
1.）我们需要“昨天”完成。
2.）我们需要它正确完成。
是的，我打算学习VHDL，但不幸的是，由于我的其他工作职责，这将花费我相当多的时间。
我只想在这里寻找一些快速的意见，谢谢你的回复。



以下为原文

I come from "the land of Altera" and schematic based logic, so VHDL is very new to me. 
 
Why this code?
I'm presently looking at some old (company product) logic because they need a new feature added.  Unfortuantely the guys that created this mess are long gone.  I've determined that any slight change causes the new compiled logic to completely screw up the existing function/performance of the board in question.  Can you say timing errors?  I believe this logic needs a total rewrite, so I'm looking into outside contractors/proffessionals for this job because....
1.) We need it done "yesterday".
2.) We need it done properly.
 
Yes I plan to learn VHDL, but unfortunately this will take me considerable time due to my other job responsibilities.  I was just looking for some quick opinions here, so thanks for your responses.
 
 

当前产品使用什么FPGA？
设计更改是作为现场改装，还是用于新生产？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

What FPGA is used in the current product?  Is the design change intended as a field retro-fit, or is it intended for new production?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

所以我也被告知这个项目没有* .ucf（通用约束文件）。那么可以在这个UCF文件中定义设置和保持时间，以使这些锁存器亚化硬化？



以下为原文

So I'm also told there is no *.ucf (universal constraint file) for this project.  So can the setup and hold times be defined in this UCF file to make these latches metastable-hardened?

.UCF文件的主要功能是将包引脚分配给IO。
时序约束也放在.UCF文件中。
设置和保持时间限制不会影响亚稳态电阻。
底层硅和栅极结构表现出亚稳态电阻。
根据定义，异步输入不会考虑您在.UCF文件中定义或“强加”的任何设置和保持时间。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

The primary function of the .UCF file is to assign package pins to IOs.
Timing constraints are also placed in the .UCF file.
 
Setup and hold time timing constraints do not affect metastable resistance.  It is the underlying silicon and gate structure which manifests metastable resistance.  By definition, asynchronous inputs do not respect any setup and hold times you might define or "impose" in the .UCF file.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

digikev写道：
所以我也被告知这个项目没有* .ucf（通用约束文件）。那么可以在这个UCF文件中定义设置和保持时间，以使这些锁存器亚化硬化吗？
实际上，UCF是用户约束文件。
如果您之前设计工作中唯一的设计文件是VHDL，则必须生成带有引脚位置和基本时序信息的UCF，以便您可以重建与板上当前工作相同的FPGA实现。
。
可能需要一天左右的时间。
只有这样你才能开始进行任何修改来修复bug。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

 

digikev wrote:
So I'm also told there is no *.ucf (universal constraint file) for this project.  So can the setup and hold times be defined in this UCF file to make these latches metastable-hardened?

 
Actually, UCF is User Constraints File.


If the only design files you have from the previous design work is the VHDL, you will have to generate a UCF with pin locations and basic timing information, so that you can rebuild an FPGA implementation that does the same as the current one on the board. Might take a day or so. Only then can you start to put any changes in to fix the bug.
 

------------------------------------------
"If it don't work in simulation, it won't work on the board."