怎么从ISE内部浏览体系结构特定元素

我的设计驱动一个外部SDRAM，它从控制状态机的相位相位计时。
Withclock倒置::
分配SDRAM_CLK = ~FX2_CLK;
我收到以下错误：
路由 -  CLK Net：FX2_CLK0_BUFGP可能有过多的偏移，因为0 CLK引脚和1个NON_CLK引脚无法使用CLK模板进行路由。
没有时钟反转：
分配SDRAM_CLK = FX2_CLK;
我没有警告。
我尝试过使用其他帖子中建议的BUFG，但得到的结果相似：
BUFG bufg_inst（FX2_CLK1，~FX2_CLK0）;
我觉得我的时钟配置出现了根本性的错误。
在这个相对较慢（48MHz）的设计中，我似乎不必采用DCM来获得两相时钟。
我想要的是以下内容：
但我不确定如何明确指出这一点。
是否有BUFG的反转版本？
有没有一种简单的方法可以从ISE内部浏览体系结构特定元素（如BUFG）？
我正在使用verilog作为我的HDL。
任何建议的tiA。
-芦苇



以下为原文

My design drives an external SDRAM which is clocked on the oposite phase from a controlling state machine. With clock inversion: :

assign SDRAM_CLK = ~FX2_CLK;

I get the following error:
Route - CLK Net:FX2_CLK0_BUFGP may have excessive skew because 0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

With no clock inversion:
assign SDRAM_CLK = FX2_CLK;
I have no warnings. I've tried using a BUFG as suggested in some other posts, but get similar results:

BUFG bufg_inst(FX2_CLK1, ~FX2_CLK0);

I have the feeling that I'm doing something fundamentally wrong with my clock configuration. It doesn't seem as though I should have to resort to a DCM to get a two phase clock  on this relatively slow (48MHz) design. What I would like is something like the following:




But I'm not sure how to specify this unambiguously. Is there an inverting version of BUFG? Is there an easy way to browse the architecture specific elements (like BUFG) from inside the ISE?  I'm using verilog as my HDL.
TIA for any suggestions. -Reed