如何在IOB中使用DDR三态多路复用器？

查看Spartan-3的IOB结构（图10.1 UG331），它显示三态路径具有与数据路径大致相同的DDR功能。
我想要做的事情（简化一点）是T1 ='1'，T2 ='0'，时钟到OTCLK1,180deg版本到OTCLK2，O1绕过数据DDR组件。
这应该只在周期的后半段驱动输出。
即，如果OTCLK1为100MHz，则输出引脚将在每个周期结束时驱动5ns。
我想这样做的原因是连接到SRAM并具有快速读取 - >写入转换。
只有写入的数据需要在周期的后半部分存在（> = 5ns），不应该在周期的前半部分驱动，因为SRAM可能尚未释放数据总线。
它在文档中说，DDR输出功能不能被推测 - 它必须是明确的。
OFDDRSE元素可用于IOB中的数据路径，但我找不到更“完整”的元素，其中还包含三态路径（OFDDRTRSE只有简单的三态路径）。
我尝试使用OFDDRSE并使用它来控制三态上的启用，毫不奇怪它不起作用。
CoreGen也没有任何东西。
是否有可用于公开此功能的核心元素？
如果没有人应该如何使用此功能？
谢谢



以下为原文

Looking at the IOB structure for the Spartan-3 (Fig10.1 UG331), It shows the tristate path as having DDR functionality much the same as the data path. What I want to do (simplified a bit) is have T1='1', T2='0', clock onto OTCLK1, 180deg version onto OTCLK2, and O1 bypassing the Data DDR componentry. This should only drive the output for second half of the cycle. i.e. if OTCLK1 is 100MHz, then the output pin will be driven for the 5ns at the end of each cycle.

The reason I want to do this is to interface to an SRAM and have quick read->write transitions. The data for the write only needs to be present for the second half of the cycle (for >=5ns), it shouldn't be driven for the first half of the cycle because the SRAM may not have released the databus yet.

It says in the documentation, that DDR output functionality can not be infered - it must be explicit. The OFDDRSE element is available for the data path in the IOB, but I can not find a more 'complete' element which also includes the Tristate path (OFDDRTRSE only has the simple tristate path). I tried using the OFDDRSE and using it to control the enable on the tristate and unsurprisingly it wouldn't work. CoreGen didn't have anything either.

Is there a core element I can use to expose this functionality? And if not how is anyone supposed to use this feature?

thanks