如何为一个计时器编写一个程序

嗨，
您唯一需要的是查看您的时钟频率并计算： 
例如，如果clk f = 50MHz（T = 20ns） 
6.4us = 6400ns => 6400/20 = 320
- 在您的程序中使用适当的值为输入端口实例化模块：
u001：timeInterval_reg
通用地图（REGWIDTH => 9）
港口地图（ 
clk_out => clk1，clk_period =>“100111111”， 
en =>'1'，clk => clk，rst_n => RST_n
）;
当时间间隔到期时，该模块产生一个时钟输出脉冲。
- 描述：时间间隔的模数。
- 当clk_period间隔到期时生成'clk_out'信号
- 只需要计算需要多少个时钟
图书馆IEEE;
使用IEEE.std_logic_1164.all;
使用IEEE.std_logic_unsigned.ALL;
ENTITY timeInterval_reg IS
GENERIC（REGWIDTH：integer：= 8）;
PORT（clk_out：OUT std_logic; 
clk_period：IN std_logic_vector（REGWIDTH-1 downto 0）; 
EN：IN std_logic; 
clk：IN std_logic; 
rst_n：IN std_logic 
）;
结构rtl of timeInterval_reg是
signal wrap：std_logic：='0';
信号计数：std_logic_vector（REGWIDTH-1 downto 0）;
开始 
进程（clk，rst_n） 
开始 
if（rst_n ='0'）然后 
数'0'）; 
换行'0'）; 
其他 
包
在原帖中查看解决方案



以下为原文

Hi,
 
The only thing you need is to see what is your clock frequency and calculate:
        for example if clk f = 50MHz   (T=20ns)
        6.4us = 6400ns   => 6400/20 = 320 
 
 
-- in your program instantiate the modul with proper values to the input ports:
 
 u001: timeInterval_reg
GENERIC MAP(REGWIDTH => 9)
PORT MAP(  
                    clk_out      => clk1,
                    clk_period => "100111111", 
                    en              => '1',
                    clk             => clk,
                    rst_n         => RST_n
 );
 
 This module generates output pulse long one clock, when time interval expires. 
 
--         Description: Modul for time interval.--                      generates 'clk_out' signal when clk_period interval expires--                      just need to calculate how many clocks are neededlibrary IEEE;use IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.ALL;ENTITY timeInterval_reg ISGENERIC(REGWIDTH : integer := 8);PORT(   clk_out    : OUT std_logic;        clk_period : IN  std_logic_vector(REGWIDTH-1 downto 0);        en         : IN  std_logic;        clk        : IN  std_logic;        rst_n      : IN  std_logic     );architecture rtl of timeInterval_reg issignal wrap : std_logic:= '0';signal count : std_logic_vector(REGWIDTH-1 downto 0);begin    process (clk, rst_n)    begin    if (rst_n = '0') then        count <= (OTHERS => '0');        wrap <= '0';    else if rising_edge(clk) then        if (en = '1') then            if (count = clk_period) then                wrap<='1';                count <= (OTHERS => '0');            else                wrap <= '0';                count <= count+1;            end if;        else            wrap <= '0';        end if;    end if;    end if;    end process;    clk_out <= wrap;end rtl;
 
  
View solution in original post

嗨，
您唯一需要的是查看您的时钟频率并计算： 
例如，如果clk f = 50MHz（T = 20ns） 
6.4us = 6400ns => 6400/20 = 320
- 在您的程序中使用适当的值为输入端口实例化模块：
u001：timeInterval_reg
通用地图（REGWIDTH => 9）
港口地图（ 
clk_out => clk1，clk_period =>“100111111”， 
en =>'1'，clk => clk，rst_n => RST_n
）;
当时间间隔到期时，该模块产生一个时钟输出脉冲。
- 描述：时间间隔的模数。
- 当clk_period间隔到期时生成'clk_out'信号
- 只需要计算需要多少个时钟
图书馆IEEE;
使用IEEE.std_logic_1164.all;
使用IEEE.std_logic_unsigned.ALL;
ENTITY timeInterval_reg IS
GENERIC（REGWIDTH：integer：= 8）;
PORT（clk_out：OUT std_logic; 
clk_period：IN std_logic_vector（REGWIDTH-1 downto 0）; 
EN：IN std_logic; 
clk：IN std_logic; 
rst_n：IN std_logic 
）;
结构rtl of timeInterval_reg是
signal wrap：std_logic：='0';
信号计数：std_logic_vector（REGWIDTH-1 downto 0）;
开始 
进程（clk，rst_n） 
开始 
if（rst_n ='0'）然后 
数'0'）; 
换行'0'）; 
其他 
包



以下为原文

Hi,
 
The only thing you need is to see what is your clock frequency and calculate:
        for example if clk f = 50MHz   (T=20ns)
        6.4us = 6400ns   => 6400/20 = 320 
 
 
-- in your program instantiate the modul with proper values to the input ports:
 
 u001: timeInterval_reg
GENERIC MAP(REGWIDTH => 9)
PORT MAP(  
                    clk_out      => clk1,
                    clk_period => "100111111", 
                    en              => '1',
                    clk             => clk,
                    rst_n         => RST_n
 );
 
 This module generates output pulse long one clock, when time interval expires. 
 
--         Description: Modul for time interval.--                      generates 'clk_out' signal when clk_period interval expires--                      just need to calculate how many clocks are neededlibrary IEEE;use IEEE.std_logic_1164.all;USE IEEE.std_logic_unsigned.ALL;ENTITY timeInterval_reg ISGENERIC(REGWIDTH : integer := 8);PORT(   clk_out    : OUT std_logic;        clk_period : IN  std_logic_vector(REGWIDTH-1 downto 0);        en         : IN  std_logic;        clk        : IN  std_logic;        rst_n      : IN  std_logic     );architecture rtl of timeInterval_reg issignal wrap : std_logic:= '0';signal count : std_logic_vector(REGWIDTH-1 downto 0);begin    process (clk, rst_n)    begin    if (rst_n = '0') then        count <= (OTHERS => '0');        wrap <= '0';    else if rising_edge(clk) then        if (en = '1') then            if (count = clk_period) then                wrap<='1';                count <= (OTHERS => '0');            else                wrap <= '0';                count <= count+1;            end if;        else            wrap <= '0';        end if;    end if;    end if;    end process;    clk_out <= wrap;end rtl;
 
  

请不要推荐std_logic_arith。
请改用numeric_std。
-一个
----------------------------是的，我这样做是为了谋生。



以下为原文

Please do not recommend std_logic_arith. Use numeric_std instead.
 
-a
----------------------------Yes, I do this for a living.

你能详细说说吗？
我是VHDL的新手



以下为原文

Can you elaborate?
 
I'm new to VHDL 

bassman59写道：请不要推荐std_logic_arith。
请改用numeric_std。
-一个
亲爱的巴斯曼59，
我刚刚完成了这个主题。
你能否解释一两行中的意思 - “使用numeric_std代替”。
您是否建议使用自然或整数来表示信号？
我同意使用Natural或Integer，代码的可读性会好得多。
但是如果未定义范围，则Natural或Integer将使用32位，因为要求可能要少得多。
对于像我这样的其他论坛成员来说，如果你能为你的评论添加几行解释，那将是非常好的。
感谢你在期待。
问候，
山塔努
Shantanu Sarkarhttp：//www.linkedin.com/pub/shantanu-sarkar/0/33a/335



以下为原文

 

bassman59 wrote:
Please do not recommend std_logic_arith. Use numeric_std instead.
 
-a

 
 
 
Dear Bassman59,
 
I was just going through the thread. Can you please explain what in one or two lines what want to mean by - "Use numeric_std instead". Are you recomending to use natural or integer for the signal count? I agree using Natural or Integer the readability of the code will much better. But if range is not defined the Natural or Integer will use 32 Bits where as the requirement may be much less.
 
It will be really nice for other forum members like me if you can put few lines of explanation to your remark.
Thanking you in anticipation.
 
Regards,
Shantanu
Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335

shantanu75写道：
bassman59写道：请不要推荐std_logic_arith。
请改用numeric_std。
-一个
亲爱的巴斯曼59，
我刚刚完成了这个主题。
你能否解释一两行中的意思 - “使用numeric_std代替”。
您是否建议使用自然或整数来表示信号？
我同意使用Natural或Integer，代码的可读性会好得多。
但是如果未定义范围，则Natural或Integer将使用32位，因为要求可能要少得多。
对于像我这样的其他论坛成员来说，如果你能为你的评论添加几行解释，那将是非常好的。
感谢你在期待。
问候，
山塔努
一堆东​​西。
a）整数和自然类型不是numeric_std的一部分 - 它们是已由语言定义的类型。
b）std_logic_arith / unsigned不是ieee库，尽管Synopsys错误地将它们放在很久以前。
c）std_logic_arith根本不处理signed和unsigned之间的区别，而numeric_std修复了这些问题：signed和unsigned是numeric_std中的有用类型。
d）使用numeric_std，在你的示例代码中，你可以声明计数信号是无符号的（REGWIDTH-1 downto 0），计数器将按预期工作。
std_logic_vector和unsigned之间的转换（在终端计数比较中需要）是一个简单的类型转换。
e）购买VHDL书籍 - 自然和整数类型可以用范围约束，这有一些有用的功能。
一个是如果在模拟中，您的计数器超出范围，那么您将得到模拟错误。
其次，它可以最大限度地减少您的计数器所需的触发器数量或任何类型的触发器。
例如： 
信号计数：自然范围0到1023;
是一个十位计数器，完全按照您的预期。 
信号数：自然范围0至999;
也可以作为十位计数器实现，但如果在模拟中，您尝试为其分配值1023，您将收到错误。
这是一个非常有用的功能。
-一个
----------------------------是的，我这样做是为了谋生。



以下为原文

shantanu75 wrote:
 

bassman59 wrote:
Please do not recommend std_logic_arith. Use numeric_std instead.
 
-a

 
 
 
Dear Bassman59,
 
I was just going through the thread. Can you please explain what in one or two lines what want to mean by - "Use numeric_std instead". Are you recomending to use natural or integer for the signal count? I agree using Natural or Integer the readability of the code will much better. But if range is not defined the Natural or Integer will use 32 Bits where as the requirement may be much less.
 
It will be really nice for other forum members like me if you can put few lines of explanation to your remark.
Thanking you in anticipation.
 
Regards,
Shantanu

A handlful of things.
 
a) integer and natural types are not part of numeric_std -- they are types already defined by the language.
 
b) std_logic_arith/unsigned are not ieee libraries, even though Synopsys made the mistake of putting them there ages ago.
 
c) std_logic_arith does not handle the distinctions between signed and unsigned well at all, and numeric_std fixes those problems: signed and unsigned are useful types in numeric_std. 
 
d) Using numeric_std, in your example code you can declare the count signal to be unsigned(REGWIDTH-1 downto 0) and the counter will work as expected. The conversion between std_logic_vector and unsigned, which you will need in your terminal count comparison, is a simple typecast.
 
e) Buy a VHDL book -- the natural and integer types can be constrained with ranges, which has a couple of useful features. One is that if in simulation, your counter exceeds the range, then you will get a simulation error. Second, it minimizes the number of flip-flops needed for your counter or whatever uses that type. For example:
 
    signal count : natural range 0 to 1023; 
 
is a ten-bit counter, exactly as you'd expect.
 
    signal count : natural  range 0 to 999;
 
is also implemented as a ten-bit counter, but if in simulation you try to assign it the value 1023 you will get an error. This is a very useful feature.
 
-a
----------------------------Yes, I do this for a living.

亲爱的巴斯曼59，感谢“少数几件事”。
我认为它不仅对我有帮助，而且对许多成员也有帮助。
但我仍然有一个问题 - 在NUMERIC_STD包中，SIGNED和UNSIGNED被声明为 -  STD_LOGIC的TYPE UNSIGNED ISRR（自然范围）;
类型已签名是STD_LOGIC的阵列（自然范围）;如果我没有错，则SIGNED始终采用2'complimet格式，而UNSIGNED将永远不会给出2的赞美结果。
我是对的吗？现在我的主要问题 - 在我不需要任何负值的特定代码中，即不需要UNSIGNED  - 就像Counter一样。
在这样的代码中，使用SIGNED（REGWIDTH-1 downto 0）和STD_LOGIC_VECTOR（REGWIDTH-1 downto 0）之间有什么区别？
有什么优点或缺点？
如在PACKAGE std_logic_1164中，STD_LOGIC_VECTOR被声明为-TYPE STD_LOGIC_VECTOR是STD_LOGIC的ARRAY（自然范围）;并且根据声明我找不到STD_LOGIC_VECTOR和UNSIGNED之间的任何区别。如果你可以再放一些灯，那将会非常好
就此而言。
我还要求其他高级论坛成员发表意见。
感谢您的期待。回答，Shantanu
Shantanu Sarkarhttp：//www.linkedin.com/pub/shantanu-sarkar/0/33a/335



以下为原文

Dear Bassman59,Thanks for “A handful of things”. I think its not only helpful to me but also going to be helpful to lots of members. But still I am having a question in my mind – In the package NUMERIC_STD, SIGNED and UNSIGNED are declared as –  TYPE UNSIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;   TYPE SIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; If I am not wrong SIGNED is always in 2’complimet format, where as UNSIGNED will never give a result in 2's compliment. Am I right? Now my main question – In a particular code where I don’t need any negative value, i.e. UNSIGNED is not required – Like in case of Counter. In such codes what is the difference between using SIGNED (REGWIDTH-1 downto 0) and STD_LOGIC_VECTOR (REGWIDTH-1 downto 0)? What are the advantages or disadvantages? As In the PACKAGE std_logic_1164, STD_LOGIC_VECTOR is declared as –TYPE STD_LOGIC_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;And according to the declaration I cannot find any difference between STD_LOGIC_VECTOR and UNSIGNED. It’ll be really nice if you can put some more lights on this. I’ll also request other senior forum members to put their views. Thanking you in anticipation. Regards,Shantanu   Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335

我不知道为什么我的上一篇文章的格式自动改变了。
所以我重新发布帖子以提高可读性。
亲爱的巴斯曼59，
感谢“少数几件事”。
我认为它不仅对我有帮助，而且对许多成员也有帮助。
但我脑子里还有一个问题 -
在NUMERIC_STD包中，SIGNED和UNSIGNED被声明为 -  STD_LOGIC的TYPE UNSIGNED ISARRAY（自然范围）;
类型签名是STD_LOGIC的阵列（自然范围）;
如果我没有错，SIGNED始终采用2'complimet格式，而UNSIGNED永远不会给出2的赞美结果。
我对吗？
现在我的主要问题 - 在我不需要任何负值的特定代码中，即不需要UNSIGNED  - 就像Counter的情况一样。
在这样的代码中，使用SIGNED（REGWIDTH-1 downto 0）和STD_LOGIC_VECTOR（REGWIDTH-1 downto 0）之间有什么区别？
有什么优点或缺点？
如在PACKAGE std_logic_1164中，STD_LOGIC_VECTOR被声明为-TYPE STD_LOGIC_VECTOR是STD_LOGIC的ARRAY（NATURAL RANGE）;
根据声明，我找不到STD_LOGIC_VECTOR和UNSIGNED之间的任何区别。
如果你能为此增加一些亮点，那将是非常好的。
我还要求其他高级论坛成员发表意见。
感谢你在期待。
问候，
山塔努 
Shantanu Sarkarhttp：//www.linkedin.com/pub/shantanu-sarkar/0/33a/335



以下为原文

I dont know the reason why the formating of my last post automatically changed. So I am resending my post for better readability.
 
Dear Bassman59,
 Thanks for “A handful of things”. I think its not only helpful to me but also going to be helpful to lots of members. But still I am having a question in my mind –


In the package NUMERIC_STD, SIGNED and UNSIGNED are declared as –  TYPE UNSIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;   TYPE SIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;


 
If I am not wrong SIGNED is always in 2’complimet format, where as UNSIGNED will never give a result in 2's compliment. Am I right?

Now my main question – In a particular code where I don’t need any negative value, i.e. UNSIGNED is not required – Like in case of Counter. In such codes what is the difference between using SIGNED (REGWIDTH-1 downto 0) and STD_LOGIC_VECTOR (REGWIDTH-1 downto 0)? What are the advantages or disadvantages?
 As In the PACKAGE std_logic_1164, STD_LOGIC_VECTOR is declared as –TYPE STD_LOGIC_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; And according to the declaration I cannot find any difference between STD_LOGIC_VECTOR and UNSIGNED.
 
It’ll be really nice if you can put some more lights on this. I’ll also request other senior forum members to put their views. Thanking you in anticipation.

Regards,
Shantanu
   
 
 
Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335

shantanu75写道：亲爱的巴斯曼59，感谢“一把事”。
我认为它不仅对我有帮助，而且对许多成员也有帮助。
但我仍然有一个问题 - 在NUMERIC_STD包中，SIGNED和UNSIGNED被声明为 -  STD_LOGIC的TYPE UNSIGNED ISRR（自然范围）;
类型已签名是STD_LOGIC的阵列（自然范围）;如果我没有错，则SIGNED始终采用2'complimet格式，而UNSIGNED将永远不会给出2的赞美结果。
我是对的吗？是的，绝对正确 - 签名是2的恭维。
无符号也不能具有小于零的值。
现在我的主要问题 - 在我不需要任何负值的特定代码中，即不需要UNSIGNED  - 就像Counter的情况一样。
在这样的代码中，使用SIGNED（REGWIDTH-1 downto 0）和STD_LOGIC_VECTOR（REGWIDTH-1 downto 0）之间有什么区别？
有什么优点或缺点？
如在PACKAGE std_logic_1164中，STD_LOGIC_VECTOR被声明为-TYPE STD_LOGIC_VECTOR是STD_LOGIC的ARRAY（自然范围）;并且根据声明我找不到STD_LOGIC_VECTOR和UNSIGNED之间的任何区别。如果你可以再放一些灯，那将会非常好
就此而言。
我还要求其他高级论坛成员发表意见。
感谢您的期待。回答，Shantanu
区别在于unsigned vs std_logic_vector的声明 - 它是如何解释这些向量的值。
numeric_std的无符号类型（以及有符号类型）的优点是你可以直接对它进行数学运算。
std_logic_vectors只是一个位数组，不代表数值。
考虑以下： 
signal C_slv：std_logic_vector（3 downto 0）：=“1111”;
C_slv有什么价值？
是15吗？
-1？
取决于它是未签名还是签名！
如果您使用numeric_std中的那些类型，则没有歧义。
这是std_logic_arith可以咬你的地方： 
信号Z_sv：std_logic_vector（3 downto 0）; 
信号A_sv：std_logic_vector（3 downto 0）; 
Z_sv定义了两个+函数，一个用于有符号值，另一个用于无符号，你的VHDL编译器不知道使用哪一个，因为它不知道“1010”是有符号还是无符号，并且它将引发错误。
如果您的实体要求您处理有符号和无符号数字，情况会更糟......如果同时使用std_logic_unsigned和std_logic_signed，它只会混淆工具。
numeric_std的signed和unsigned类型没有缺点。
转换为std_logic_vector和从std_logic_vector转换就像使用类型转换一样简单。
对于Xilinx而言，他们的文档，示例和代码模板仍然使用ieee.std_logic_arith.all，这是非常羞耻和尴尬的。
并使用ieee.std_logic_unsigned.all;
甚至反对所有建议以及各种用户提交的所有增强请求。
-一个
----------------------------是的，我这样做是为了谋生。



以下为原文

shantanu75 wrote:
Dear Bassman59,Thanks for “A handful of things”. I think its not only helpful to me but also going to be helpful to lots of members. But still I am having a question in my mind – In the package NUMERIC_STD, SIGNED and UNSIGNED are declared as –  TYPE UNSIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;   TYPE SIGNED IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;

 If I am not wrong SIGNED is always in 2’complimet format, where as UNSIGNED will never give a result in 2's compliment. Am I right? 

Yes, absolutely right -- signed is 2's compliment. Unsigned also cannot have a value less than zero.
 
 

Now my main question – In a particular code where I don’t need any negative value, i.e. UNSIGNED is not required – Like in case of Counter. In such codes what is the difference between using SIGNED (REGWIDTH-1 downto 0) and STD_LOGIC_VECTOR (REGWIDTH-1 downto 0)? What are the advantages or disadvantages? As In the PACKAGE std_logic_1164, STD_LOGIC_VECTOR is declared as –TYPE STD_LOGIC_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;And according to the declaration I cannot find any difference between STD_LOGIC_VECTOR and UNSIGNED. It’ll be really nice if you can put some more lights on this. I’ll also request other senior forum members to put their views. Thanking you in anticipation. Regards,Shantanu   

 
The difference is not in the declaration of unsigned vs std_logic_vector -- it is in how the libraries interpret the values of these vectors.
 
The advantage of numeric_std's unsigned type (as well as the signed type) is that you can do math on it directly. std_logic_vectors are simply an array of bits and do not represent numerical values. Consider the following:
 
    signal C_slv : std_logic_vector(3 downto 0) := "1111";
 
What value is C_slv? Is it 15? -1? Depends on whether it is unsigned or signed! If you use those types from numeric_std, there is no ambiguity. Here is where std_logic_arith can bite you:
 
    signal Z_sv : std_logic_vector(3 downto 0);
    signal A_sv : std_logic_vector(3 downto 0);
 
    Z_sv <= A_sv + "1010";
 
The above assignment is ambiguous. std_logic_arith defines two + functions, one for signed values and another for unsigned, and your VHDL compiler cannot know which one to use because it does not know whether "1010"  is signed or unsigned, and it will throw an error.
 
It gets even worse if your entity requires you to handle both signed and unsigned numbers ... it just confounds the tools if you use both std_logic_unsigned and std_logic_signed.
 
There are no disadvantages to numeric_std's signed and unsigned types. Converting to and from std_logic_vector is as simple as a typecast.
 
 It is to Xilinx' great shame and embarrassment that their documentation, examples and code templates still use ieee.std_logic_arith.all; and use ieee.std_logic_unsigned.all; even against all recommendations and with all of the enhancement requests submitted by various users.
 
-a
----------------------------Yes, I do this for a living.