Verilog设计AD自动采集模块异常

AdSram模块
Clk    使用CPLD时钟60MHz
Rst_n  控制模块采集开启及关闭
Freq   接单片机PWM控制Ad采集速度
外接2片2048*16 SRAM
output reg SramCs0,
output reg SramCs1,
output reg SramRd,
output reg SramWd,
output reg[20:0] SramA,
接2片AD9238双通道12AD,总共4路AD输入通道
output reg AdClk,
output reg AdA,
output reg AdB,
DoneFlag  采集完成标记，通知单片机中断
问题：使用单片机PWM接Freq，只有偶尔能采集？接CPLD的60MHz分频的信号，可以正常采集。
求为什么会出现这个想象，是代码哪里设计有什么问，望朋友帮忙看下。
[AppleScript] 纯文本查看 复制代码
module AdSram(input Clk,input Rst_n,input Freq,output reg AdClk,output reg AdA,output reg AdB,output reg SramCs0,output reg SramCs1,output reg SramRd,output reg SramWd,output reg[20:0] SramA,output reg DoneFlag);//`define S_MAX_NUM 20'hFFFFF `define S_MAX_NUM 5 parameter WAIT   = 0;parameter DONE   = 1;parameter ADA1RD = 2;parameter ADA1WR = 3;parameter ADB1RD = 4;parameter ADB1WR = 5;parameter ADA2RD = 6;parameter ADA2WR = 7;parameter ADB2RD = 8;parameter ADB2WR = 9;parameter IDLE   = 10;parameter WAITF1 = 11;reg  [3:0] state_c,state_n;wire IDLE_WAIT;wire WAIT_ADA1RD;wire ADA1RD_ADA1WR;wire ADA1WR_ADB1RD;wire ADB1RD_ADB1WR;wire ADB1WR_ADA2RD;wire ADA2RD_ADA2WR;wire ADA2WR_ADB2RD;wire ADB2RD_ADB2WR;wire ADB2WR_WAITF1;wire WAITF1_WAIT;wire WAIT_DONE;// Input Freq Sync reg freq,freq0;always  @(posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginfreq  <= 1'b1;freq0 <= 1'b1;endelse beginfreq0  <= Freq;freq   <= freq0;endendreg [3:0] setp_cnt;always  @(posedge Clk or negedge Rst_n)begin    if(Rst_n==1'b0)begin        setp_cnt <= 0;end    else begincase(state_c)ADA1RD,ADA1WR,ADA2RD,ADA2WR,ADB1RD,ADB1WR,ADB2RD,ADB2WR:setp_cnt <= setp_cnt + 1;default:setp_cnt <= 0;endcaseendendreg [19:0] AddCnt;always  @(posedge Clk or negedge Rst_n)begin    if(Rst_n == 1'b0)begin        AddCnt <= 0;end    else begincase(state_c)DONE:AddCnt <= 0;default:beginif(setp_cnt == 7)AddCnt <= AddCnt + 1;endendcaseendendalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginstate_c <= IDLE;endelse beginstate_c <= state_n;endendalways @(*)begincase(state_c)IDLE:beginif(IDLE_WAIT)beginstate_n = WAIT;endelse beginstate_n = state_c;endendWAIT:beginif(WAIT_ADA1RD)beginstate_n = ADA1RD;endelse if(WAIT_DONE)beginstate_n = DONE;endelse beginstate_n = state_c;endendDONE:beginstate_n = state_c;endADA1RD:beginif(ADA1RD_ADA1WR)beginstate_n = ADA1WR;endelse beginstate_n = state_c;endendADA1WR:beginif(ADA1WR_ADB1RD)beginstate_n = ADB1RD;endelse beginstate_n = state_c;endendADB1RD:beginif(ADB1RD_ADB1WR)beginstate_n = ADB1WR;endelse beginstate_n = state_c;endendADB1WR:beginif(ADB1WR_ADA2RD)beginstate_n = ADA2RD;endelse beginstate_n = state_c;endendADA2RD:beginif(ADA2RD_ADA2WR)beginstate_n = ADA2WR;endelse beginstate_n = state_c;endendADA2WR:beginif(ADA2WR_ADB2RD)beginstate_n = ADB2RD;endelse beginstate_n = state_c;endendADB2RD:beginif(ADB2RD_ADB2WR)beginstate_n = ADB2WR;endelse beginstate_n = state_c;endendADB2WR:beginif(ADB2WR_WAITF1)beginstate_n = WAITF1;endelse beginstate_n = state_c;endendWAITF1:beginif(WAITF1_WAIT)beginstate_n = WAIT;endelse beginstate_n = state_c;endenddefault:beginstate_n = IDLE;endendcaseendassign IDLE_WAIT     = (state_c == IDLE)   && (Rst_n == 1);assign WAIT_DONE     = (state_c == WAIT)   && (AddCnt == `S_MAX_NUM);assign WAIT_ADA1RD   = (state_c == WAIT)   && (freq  == 0) && (AddCnt  < `S_MAX_NUM);assign ADA1RD_ADA1WR = (state_c == ADA1RD) && (setp_cnt == 0);assign ADA1WR_ADB1RD = (state_c == ADA1WR) && (setp_cnt == 1);assign ADB1RD_ADB1WR = (state_c == ADB1RD) && (setp_cnt == 2);assign ADB1WR_ADA2RD = (state_c == ADB1WR) && (setp_cnt == 3);assign ADA2RD_ADA2WR = (state_c == ADA2RD) && (setp_cnt == 4);assign ADA2WR_ADB2RD = (state_c == ADA2WR) && (setp_cnt == 5);assign ADB2RD_ADB2WR = (state_c == ADB2RD) && (setp_cnt == 6);assign ADB2WR_WAITF1 = (state_c == ADB2WR) && (setp_cnt == 7);assign WAITF1_WAIT   = (state_c == WAITF1) && (freq  == 1);// AD Outputalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginAdClk <= 1'b0;endelse begincase(state_c)ADA1RD,ADA1WR,ADB1RD,ADB1WR:AdClk <= 1'b1;default:AdClk <= 1'b0;endcaseendendalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginAdA <= 1'b1;endelse begincase(state_c)ADA1RD,ADA1WR,ADA2RD,ADA2WR:AdA <= 1'b0;default:AdA <= 1'b1;endcaseendendalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginAdB <= 1'b1;endelse begincase(state_c)ADB1RD,ADB1WR,ADB2RD,ADB2WR:AdB <= 1'b0;default:AdB <= 1'b1;endcaseendend// Sram Outalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginSramCs0 <= 1'bz;endelse begincase(state_c)ADA1RD,ADA1WR,ADB1RD,ADB1WR:SramCs0 <= 1'b0;default:SramCs0 <= 1'b1;endcaseendendalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginSramCs1 <= 1'bz;endelse begincase(state_c)ADA2RD,ADA2WR,ADB2RD,ADB2WR:SramCs1 <= 1'b0;default:SramCs1 <= 1'b1;endcaseendendalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginSramRd <= 1'bz;endelse beginSramRd <= 1'b1;endendalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginSramWd <= 1'bz;endelse begincase(state_c)ADA1RD,ADA2RD,ADB1RD,ADB2RD:SramWd <= 1'b0;default:SramWd <= 1'b1;endcaseendend//Sram A[19:0]always @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginSramA[19:0] <= 20'bz;endelse begin//if(state_c == WAIT)beginSramA[19:0] <= AddCnt[19:0];//endendend//Sram A[20]always @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginSramA[20] <= 1'bz;endelse begincase(state_c)ADA1RD,ADA1WR,ADA2RD,ADA2WR:SramA[20] <= 1'b0;default:SramA[20] <= 1'b1;endcaseendend// DoneFlagalways @ (posedge Clk or negedge Rst_n)beginif(Rst_n == 1'b0)beginDoneFlag <= 1'b0;endelse begincase(state_c)DONE:DoneFlag <= 1'b1;default:DoneFlag <= 1'b0;endcaseendendendmodule