怎么使用FPGA的无形IO引脚添加测试点

重置是否同步？
抖？
它符合你的所有逻辑吗？
（这都假设您正在谈论系统重置而不是脉冲PROG。）
_____________________________________________________________________________这个世界上有10种人。
那些懂二进制的人，有些不懂的人。



以下为原文

Is the reset synchronous?  Debounced?  Does it go to all of your logic?
 
(This is all assuming that you're talking about a system reset as opposed to pulsing PROG.) 
_____________________________________________________________________________
There are 10 kinds of people in this world.  Those who understand binary, and those who don't.

哦，您是否尝试过模拟（理想情况下为Post-PAR）重置？
_____________________________________________________________________________这个世界上有10种人。
那些懂二进制的人，有些不懂的人。



以下为原文

Oh, and have you tried simulating (Post-PAR ideally) the reset?_____________________________________________________________________________
There are 10 kinds of people in this world.  Those who understand binary, and those who don't.

嘿，非常感谢你。
是的，重置是同步的，去抖动，它贯穿整个逻辑。
我的设计，包括系统重置，在没有测试点时可以很好地工作。
所以，对我来说，向顶级vhdl模块添加一些额外端口会导致这样的问题真的很奇怪。
更重要的是，它很奇怪，因为我发现并非所有信号分配都会在该问题中结束，例如：
以下的配置不会造成任何麻烦
TP1 signalB，signalC，signalD是在逻辑的某些过程中使用的信号。
TP2 --TP1分配给引脚K2
TP3 --TP1分配给引脚K1
TP4 --TP1分配给引脚K6
虽然以下内容最终出现在前面提到的问题中
TP1 signalB，signalC，signalD是在逻辑的某些过程中使用的信号。
TP2 --TP1分配给引脚K2
TP3 --TP1分配给引脚K1
TP4 --TP1分配给引脚K6。
当分配不同于signalA，signalB，signalC，signalD的信号时，设计表现奇怪
无论如何，我会尝试Post-PAR模拟（尽管我从未使用它）。
如果您在重播后有任何其他建议，我将非常感谢您通知我。
顺便说一句，好听的说;
关于这个世界上的10种人。
真是太棒了！
谢谢。



以下为原文

Hey, thank you very much indeed.
Yes, the Reset is synchronous, debounced and it goes through the whole logic. My design, including the system Reset,  works quite well when no test points are present. So, for me it is really weird that the addition of some extra ports to the top vhdl module causes such issue. What is more, it is weird because I have found that not all signal assignment end up in that issue, for example:
 
The following assingment does not cause any trouble
TP1 <= signalA; --TP1 is assigned to pin L3. signalA,signalB,signalC,signalD are signals used in some processes of the logic.
TP2 <= signalB; --TP1 is assigned to pin K2
TP3 <= signalC; --TP1 is assigned to pin K1
TP4 <= signalD; --TP1 is assigned to pin K6
 
While the following one end up in the issue mentioned before

TP1 <= signalA; --TP1 is assigned to pin L3. signalA,signalB,signalC,signalD are signals used in some processes of the logic.
TP2 <= signalB; --TP1 is assigned to pin K2
TP3 <= signalC; --TP1 is assigned to pin K1
TP4 <= signalE; --TP1 is assigned to pin K6. When assigning a signal different from signalA,signalB,signalC,signalD the desing behaves oddly
 
Any way, I'll try Post-PAR simulating (despite I have never used it). If you had any other suggestion after this replay, I would really appreciate you to let me know.
 
By the way, nice saying; about the 10 kinds of people in this world. just brilliant!
Thanks.