DCM波形第一次和第二次重置出现不同

你好......首先要确保你的模拟器的分辨率是PS。
这可能是您的问题，但如果不是，我们将需要有关您的DCM的更多详细信息。希望这有助于... George



以下为原文


Hello....

First of all make sure that the resolution of your simulator is PS. This is probably your problem but if it is not we will need more details about your DCM.

Hope this helps...

George

唐，
尝试让您的模拟运行更长时间。
在这种情况下DCM（或其模型）很可能仍然处于通过调整延迟抽头获取锁定的过程中。
它可能比您允许锁定的时间长得多。
通常，在获得锁定之前，您不应该依赖DCM的输出。
这包括模拟和真实的硬件设计。
您可能会发现在模拟中查看LOCKED输出也很有用。
当您再次重置DCM时，DCM正在尝试锁定。
此应用说明提供了有关DCM如何工作的良好背景：
http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf（在Spartan-3 FPGA中使用数字时钟管理器（DCM））
祝你好运，
BT
==编辑
有关延迟分接过程的更好说明，请参见第2页
http://www.xilinx.com/support/documentation/application_notes/xapp174.pdf（在Spartan-II FPGA中使用延迟锁定循环）请记住，DCM是具有附加功能的DLL的超集（例如，频率合成）
）
消息由timpe在01-15-2008 02:39 AM编辑



以下为原文

Don, Try letting your simulation run for much longer.The DCM (or model thereof in this case) is very likely still in the process of acquiring lock by adjusting the delay taps.It likely takes much longer than you've allowed to lock.In general, you shouldn't rely on the DCM's output until it has achieved lock. This includes both simulation and a real hardware design. You will likely find it also useful to look at the LOCKED output in the simulation. The DCM was in the process of attempting to lock when you reset it again. This app note provides good background on how a DCM works:http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf (Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs) Good luck,bt == edita better description of the delay tap process is found here on page 2http://www.xilinx.com/support/documentation/application_notes/xapp174.pdf (Using Delay-Locked Loops in Spartan-II FPGAs)
Keep in mind that a DCM is a superset of a DLL with additional functionality (e.g. frequency synthesis)
 

Message Edited by timpe on 01-15-2008 02:39 AM

嗨！问题现在解决了。非常感谢你的帮助。



以下为原文

Hi!

The problem is solved now.Thank you so much for your help.

我很高兴听到它。
感谢您的反馈。
在数据表中查看器件的相关DCM参数也是一个好主意。
这些因家庭而异，但可以让您对使用和要求（输入和输出范围，重置要求等）有所了解。
还有一些有用的答案记录，包括：http：//www.xilinx.com/support/answers/18181.htm（Virtex-II / -II Pro / -4 / -5  - 级联两个DCM的规则是什么
系列？）http://www.xilinx.com/support/answers/14425.htm(Virtex-II / Pro / 4/5 DCM  - 强烈建议配置有外部或内部反馈的DCM后配置重置（
VHDL / Verilog））http：//www.xilinx.com/support/answers/13756.htm（Virtex-II / -II Pro，DCM  - 什么原因导致DCM时钟输出出现相位误差，占空比失真和过度抖动（
VCCAUX，下垂，倾角，纹波，CLK2X周期）？）
干杯，BT



以下为原文

I'm glad to hear it. Thanks for the feedback.
It is also a good idea to review the device's associated DCM parameters in the datasheet. These vary by family, but can give you a good idea of usage and requirements (input and output ranges, reset requirement, etc.)
There are also useful answer records, including:
http://www.xilinx.com/support/answers/18181.htm (Virtex-II/-II Pro/-4/-5 - What are the rules for cascading two DCMs in series?)
http://www.xilinx.com/support/answers/14425.htm (Virtex-II/Pro/4/5 DCM - Resetting after configuration is strongly recommended for a DCM that is configured with external or internal feedback (VHDL/Verilog))
http://www.xilinx.com/support/answers/13756.htm (Virtex-II/-II Pro, DCM - What causes phase error, duty cycle distortion, and excessive jitter on DCM clock outputs (VCCAUX, droop, dip, ripple, CLK2X period)?)
Cheers,
bt