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在其中“变频情人”只有没有TDR功能的6 GHz的VNA线“边缘电容多项式的系数”,我愿意尽力来衡量他的PCB与我的20 GHz的VNA它具有TDR功能。
再后来乔尔说他的板需要20GHz的VNA,这意味着我被卡住,因为我只具有一个9千兆赫校准套件(85033E),其只具有固定的负载(没有滑动负载)。 但我想知道这会有多糟糕。 看一下我的9 GHz 85033E校准套件中开口的边缘电容系数,我注意到它们与26.5 GHz 85052B校准器相同。 (C0 = 49.433,C1 = -310.13C2 = 23.168C3 = -0.1596)。 这种情况让我相信它们几乎肯定是相同的部分 - 也许9 GHz频率被拒绝26.5 GHz,但这些必须是非常相似或相同的部分。 由于8720D不允许一个指定的电感值,我也不会太惊讶,如果在VNA的偏移量和/或电容系数改变85033E和85052B之间的包了一下 - 我没有检查这一点。 但是,如果1)我选择了85052B校准套件,它内置在我的8720D / 2固件)用于宽带负载到20GHz什么样的性能(或缺乏)将预期? 我想知道如果我将VNA校准到20 GHz,尽管没有滑动负载,它是否能解决频率爱好者的PCB问题。 DaveEdited:drkirkby于2013年1月25日晚上11:23 以上来自于谷歌翻译 以下为原文 In the thread "Coefficients of fringing capacitance polynomial", where "Frequency Lover" only has a 6 GHz VNA without the TDR function, I offered to try to measure his PCB with my 20 GHz VNA which has the TDR function. Then later Joel said his board needs a 20 GHz VNA, which means I'd be stuck as I only have a 9 GHz cal kit (85033E), which only has a fixed load (no sliding load). But I wondered how bad this would be. Looking at the fringing capacitance coefficients of the opens in my 9 GHz 85033E cal kit, I note they are the same as in the 26.5 GHz 85052B cal it. (C0=49.433, C1=-310.13 C2=23.168 C3=-0.15966). That sort of leads me to believe they are almost certainly the same parts - perhaps the 9 GHz ones are rejected 26.5 GHz ones, but these must be very similar or identical parts. Since the 8720D does not allow one to specify inductance values, I would not be too surprised if the offset and/or capacitance coefficients in that VNA vary a bit between the 85033E and the 85052B kits - I have not checked this. But if 1) I selected the 85052B calibration kit, which is built into the firmware of my 8720D/ 2) Used a broadband load to 20 GHz what sort of performance (or lack of) would be expected? I was wondering if it could sort out Frequency Lover's PCB issue if I calibrated the VNA to 20 GHz, despite not having a sliding load. Dave Edited by: drkirkby on Jan 25, 2013 11:23 PM |
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如果您使用TDR来连接输入连接器,那么负载不良的影响确实非常小。
负载用于表征系统的方向性,该方向性发生在相对于校准平面的负时间; 加载错误将与SMA连接器中的错误一起被门控。 据我所知,所有3.5 mm校准套件的所有内部部件都是相同的,但负载仅在其特定频率范围内进行测试和规格。 可能在15年前对负载进行了调整,因此在低频率下工作的负载也可以在高频率下正常工作。 打开和短裤是相同的,多年前,定义被标准化为al PNA,ENA等(不久前的ENA)。 在此之前,优化仅适用于6或9 Ghz。 以上来自于谷歌翻译 以下为原文 If you are using TDR to gate the input connector, then the effect of a poor load will be very small indeed. The load is used to characterize the directivity of the system, which occurs at negative time relative to the the calibration plane; error in the load will be gated out along with errors from the SMA connector. As far as I know, all the internal parts of all the 3.5 mm cal kits, are identical, but the loads are tested and spec'd only over their particual frequency range. There was a tweak to the loads maybe 15 years ago, so that the loads that work at low frquencies can also work well at high frequencies. Opens and shorts are identical, and years ago the definition were normalized for al PNA, ENA, etc (ENA not too long ago). Before that, the optimization was only for 6 or 9 Ghz. |
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> {quote:title = Dr_joel写道:} {quote}>如果你使用TDR来连接输入连接器,那么负载不良的影响确实非常小。
负载用于表征系统的方向性,该方向性发生在相对于校准平面的负时间; 加载错误将与SMA连接器中的错误一起被门控。 谢谢。 我会提议为他做这件事。 这是他的选择,但我认为即使在本科项目中,也可以接受由能力更强的设备测量的东西。 也许不同的主管可能会看到它有所不同。 通常(不仅仅是TDR),可以指定测量精度的限制,这会导致由于非理想负载导致校准不良? 我想这将在你的书的第3章中介绍,但是欢迎任何指向相关位的指针! 顺便说一句,我认为你的书的方程1.19中有一个错误。 我认为左下角的S1n应该是Sn1。 你有地方的勘误页吗? 戴夫 以上来自于谷歌翻译 以下为原文 > {quote:title=Dr_joel wrote:}{quote} > If you are using TDR to gate the input connector, then the effect of a poor load will be very small indeed. The load is used to characterize the directivity of the system, which occurs at negative time relative to the the calibration plane; error in the load will be gated out along with errors from the SMA connector. Thank you. I'll offer to do it for him then. It's his choice, but I think even in an undergraduate project, getting something measured by someone with more capable equipment is acceptable. Maybe different supervisors might see it different though. In general (not just TDR), it is possible to specify limits on the accuracy of measurements which result in poor calibration due to a non ideal load? I guess this is covered in chapter 3 of your book, but any pointers to the relevant bit would be welcome! BTW, I think there's an error in equation 1.19 of your book. S1n in the bottom left should I believe be Sn1. Do you have an errata page anywhere? Dave |
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是的,你是对的。
我会将其标记为复制/粘贴错误...我将添加该列表(到目前为止只有19个,我认为你发现了2个)。 以上来自于谷歌翻译 以下为原文 Yup, you're right. I'll mark that as a copy/paste error... I'll add that the the list (only 19 so far, I think you found 2). |
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