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我的项目设计涉及Systolic Array。 Systolic Array由几个Processing Element(PE)构成,如下面的图1所示。 如图1所示,每个PE都有一个查询字符。 图1:Systolic阵列的PE连接 因此,在我的设计中,如图2所示,PE的3位查询字符(QC)i / p连接到顶层模块的QueSec i / p,以便所有查询字符都通过Queue i / p加载到每个PE中 在平行下。 但是,由于FPGA中的i / o有限,实际没有。 由于i / p的大小,PE不能生成。 。 图2:我的心脏收缩阵列设计的顶层模块 为了克服I / O问题,我必须将QueSec i / p大小更改为3位,而不是如图2所示。但是通过使用此大小,我只能看到数据将以串行方式加载而不是并行加载。 任何人都可以给我一些想法,使用3位QueSec i / p大小和parallry中的数据插入每个PE? 非常感谢你帮助我。 以上来自于谷歌翻译 以下为原文 Hi everyone. My project design involve Systolic Array. Systolic Array is build up of several Processing Element (PE) as shown in the Figure 1 below. As shown in the Figure 1, each PE holds one Query Character. Figure 1: PE connection of Systolic Array Thus, in my design as shown in Figure 2, the 3-bit Query Character (QC) i/p for PE is connected to QueSec i/p at the top module so that all the query characters are loaded in each PE through QueSec i/p in parallel. However, due to limited i/o in FPGA, the actual no. of PEs cant be generated, because of the big size i/p. . Figure 2: Top module of my systolic array design To overcome the i/o issue, I have to change QueSec i/p size to 3-bit, not as shown in Figure 2. But by using this size i can only see that the data will be loaded serially not in parralle. Can anyone give me some idea, to use 3-bit QueSec i/p size and the data in parallry insert in each PE? Thank you very much for helping me. |
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8个回答
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我的建议是采用那个大的并行总线,并连接到串行到并行移位寄存器。我假设您的并行总线或多或少是静态的?
如果是这样,那么只需通过串行连接加载它。 不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。 以上来自于谷歌翻译 以下为原文 My recommendation is to take that big parallel bus, and connect to a serial to parallel shift register.. I'm assuming that your parallel bus is more or less static? If so, then just load it up via a serial connection. Don't forget to close a thread when possible by accepting a post as a solution. |
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@jmcclusk
这是不是说我有多个o / p从SIPO连接到SA? 但我需要使用一个i / p 静电是什么意思? 以上来自于谷歌翻译 以下为原文 @jmcclusk Doesn that mean I have more than one o/p that is connected from SIPO to SA? But I need to use one i/p What di you mean by static? |
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或多或少会出现您的查询字符不经常更改..您是否尝试设计与查询字符集合匹配的收缩管道?
如果您不需要经常更改查询字符的值,则只需使用串行加载的寄存器链来驱动查询字符值...或使用处理器总线来加载一组并行寄存器。 不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。 以上来自于谷歌翻译 以下为原文 It more or less appears that your query characters are not changed very often.. are you trying to design a systolic pipeline that matches against a collection of query characters? if you don't need to change the values of the query characters frequently, then just use a serially loaded register chain to drive the query character values... or use a processor bus to load a set of parallel registers. Don't forget to close a thread when possible by accepting a post as a solution. |
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@jmcclusk
jmcclusk写道: 您是否尝试设计与查询字符集合匹配的收缩管道? 它是一个QC与一个PE中的SS流之间的比较。 例如 QC A. SS AGCS QC并不总是一样的。 jmcclusk写道: 如果您不需要经常更改查询字符的值,则只需使用串行加载的寄存器链来驱动查询字符值...或使用处理器总线来加载一组并行寄存器。 不是SIPO或PIPO产生多个o / p? 有没有办法避免这种情况? 以上来自于谷歌翻译 以下为原文 @jmcclusk jmcclusk wrote:It is a comparision between one QC and a stream of SS in one PE. For example QC A SS AGCS QC will not always be the same. jmcclusk wrote:Dont SIPO or PIPO produces multiple o/p? Is there any method to avoid that? |
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关键问题是:您需要多久更改一次查询字符?
每个时钟周期? 或每1000个时钟周期? 如果你需要在每个时钟周期更改它,那么你有一个问题..如果它是1000或更多,那么答案很简单,只是串行移动一组查询字符,然后运行你的收集管道与该集合.. 这是批处理模式操作。 并且您可以更改批次之间的查询字符集。 不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。 以上来自于谷歌翻译 以下为原文 The key question is this: How often do you need to change the query character? every clock cycle? or every 1000 clock cycles? If you need to change it every clock cycle, then you have a problem.. if it's 1000 or more, then the answer is easy, just serially shift in a collection of query characters, and then run your systolic pipeline with that collection.. It's a batch mode operation. and you can change the query character set between batches. Don't forget to close a thread when possible by accepting a post as a solution. |
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@jmcclusk
它就像在第一个1000 clk循环中预加载QC然后在那之后计算开始? 现在我懂了 但现在我有另一个问题 根据我的理解,3位SISO意味着它由3个FF和1位i / p和o / p组成。 我可以设计具有3位i / p和o / p的SISO吗? 如果有可能FF的数量怎么样? 以上来自于谷歌翻译 以下为原文 @jmcclusk Its like preload the QC in 1st 1000 clk cycle then computation start after that right? Now I get it But now I have another question In my understanding, 3-bit SISO mean that it consist of 3 FF with 1-bit i/p and o/p. Can I design SISO with 3-bit i/p and o/p? If it possible how about the number of FF? |
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移位寄存器可以设计成任何所需的宽度。
尝试使用VHDL或Verilog中的一些简单示例,如果操作正确,可以使用泛型(或Verilog中的参数)来指定串行输入,并行输出移位寄存器链的宽度和长度。 不要忘记通过接受帖子作为解决方案来尽可能地关闭线程。 以上来自于谷歌翻译 以下为原文 shift registers can be designed with any width desired. Try some simple examples in VHDL or Verilog, and if you do it right, you can use generics ( or parameters in Verilog) to specify the width and length of a serial input, parallel output shift register chain. Don't forget to close a thread when possible by accepting a post as a solution. |
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