怎么使用命令行的非项目模式xsim VHDL testbench

大家好，
我试图在Linux上使用Vivado的VHDL项目使用命令行工作流程。
关于这个工作流程，我有三个问题：
- 目前我使用makefile来调用xvhdl，xelab和xsim。现在我只对使用xsim模拟我的VHDL代码感兴趣并在waveviewer中查看结果。
我使用外部编辑器编写VHDL代码本身。
使用makefile是首选方法还是应该使用基于Tcl的流程？
- 我无法弄清楚如何使用我当前的工作流程来使用我的VHDL测试平台（见上文）。
我确实看到了波形查看器，但所有信号都是未定义的。
目前我的项目只包含两个文件：and_gate.vhd和and_gate_tb.vhd。
如何使用我的测试平台作为AND门的激励并在waveviewer中查看输入和输出信号？
- 在我更改VHDL文件后，有没有办法让Vivado窗口保持活动状态并重新模拟？



以下为原文

Hi all,

I am trying to use a command line workflow for my VHDL project with Vivado on Linux. Regarding this workflow I have three questions:
- Currently I use a makefile to call xvhdl, xelab and xsim. For now I am only interested in simulating my VHDL code using xsim and view the result in the waveviewer. I use an external editor to write the VHDL code itself. Is using a makefile the preferred approach or should I use a Tcl based flow instead?
- I cannot figure out how to use my VHDL testbench using my current workflow (see above). I do get to see the waveform viewer but all signals are undefined. For now my project only consists of two files: and_gate.vhd and and_gate_tb.vhd. How can I use my testbench as stimulus for my AND gate and view my input and output signals in the waveviewer?
- Is there a way to keep the Vivado window alive and re-simulate after I make a change to my VHDL files?