完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
AXI_GPIO中存在一个小错误,可以防止使用电路板文件。
在Vivado / 2016.2 / data / ip / xilinx / axi_gpio_v2_0 / xgui / axigpio_v2_0.tcl中有一个额外的']'是第246行的结尾 在GPIO2接口上添加三态GPIO端口时会导致错误。 以上来自于谷歌翻译 以下为原文 There is a small bug in the AXI_GPIO that prevents the use of board files. There is an extra ']' are the end of line 246 within Vivado/2016.2/data/ip/xilinx/axi_gpio_v2_0/xgui/axigpio_v2_0.tcl It causes errors when adding a tristate GPIO port on the GPIO2 interface. |
|
相关推荐
6个回答
|
|
@ tom21091谢谢你在这里报道。
你在用什么板? 你能为我提供相同的快照吗? -Pratham ------------------------------------------------ ----------------------------------------------请注意 - 请 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K- -------------------------------------------------- ----------------------- 以上来自于谷歌翻译 以下为原文 @tom21091 Thanks for reporting this here. What is the board you are using? could you please provide me snapshot for the same? -Pratham ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
喜
这是一个很好的捕获。 如果您在尝试添加三态路径时看到任何错误消息,可以告诉我们吗? --hs -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 以上来自于谷歌翻译 以下为原文 hi, that is a good catch. can you let us know if you see any error message when trying to add the tri-state path? --hs ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
任何使用GPIO接口上所有3个三态逻辑端口的电路板都会出现此问题。
我正在使用我们为Digilent板创建的板文件。 移除额外支架后,错误消失。 这只是一个小错字导致tcl脚本混淆。 以上来自于谷歌翻译 以下为原文 The problem occurs with any board that uses all 3 tristate logical ports on the GPIO interface. I'm using the board files we create for Digilent boards. The error is gone once you remove the extra bracket. It was just a small typo that caused the tcl script to get confused. |
|
|
|
喜
让我检查并回来。 -HS -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 以上来自于谷歌翻译 以下为原文 hi, let me check and get back. -hs ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
喜
已提交针对IP tcl的变更请求。 CR ID为CR-956534。 这将在未来的IP版本中修复。 --hs -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 以上来自于谷歌翻译 以下为原文 hi, a change request against the IP tcl has been filed. The CR ID is CR-956534. This will be fixed in the future release of the IP. --hs ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
喜
此问题已在vivado的下一个版本中修复。 参考tcl修改。 --hs -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 以上来自于谷歌翻译 以下为原文 hi, this issue is fixed in the next release of vivado. refer to the tcl modification. --hs ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
|
|
|
只有小组成员才能发言,加入小组>>
2385 浏览 7 评论
2800 浏览 4 评论
Spartan 3-AN时钟和VHDL让ISE合成时出现错误该怎么办?
2264 浏览 9 评论
3336 浏览 0 评论
如何在RTL或xilinx spartan fpga的约束文件中插入1.56ns延迟缓冲区?
2433 浏览 15 评论
有输入,但是LVDS_25的FPGA内部接收不到数据,为什么?
762浏览 1评论
请问vc707的电源线是如何连接的,我这边可能出现了缺失元件的情况导致无法供电
548浏览 1评论
求一块XILINX开发板KC705,VC707,KC105和KCU1500
375浏览 1评论
1970浏览 0评论
688浏览 0评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-11-26 14:09 , Processed in 1.846946 second(s), Total 88, Slave 72 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号