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亲爱的同事，
感谢大家的所有帮助和支持。 我试图在裸机上使用Zynq（Zynq-702板）中的ARM写入数据（超过2 MB）。 大多数时候写入的数据是正确的，但有时我可以看到写入的数据不正确。 我很想知道你是否可以推荐一些方法来确保写在DDR上的数据总是与我们想写的无关，无论数据量如何。 非常感谢你。 带着敬意 以上来自于谷歌翻译 以下为原文 Dear Colleague, Thanking you all for all your help and support. I am trying to write the data(more than 2 MB) on DDR using arm in Zynq(Zynq-702 board) in bare-metal. Most of the time data written is correct but sometime I can see that data written is not correct. I am curious to know if you could recommend some way to make sure that data written on DDR is always exactly what we want to write irrespective of the amount of data. Thanking you very much. With regards 
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5个回答
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您是在尝试始终从处理器写入/读取，还是从PL写入并从处理器读取。
如果是前者，除硬件问题外，它应该始终没有问题。 运行一个软件内存测试器，看看你是否有可靠性问题。如果是后者，那么它可能与缓存有关。 你使用哪个AXI端口，如何通知处理器/缓存ddr更新，即缓存无效？ - 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 Are you trying to write/read from the processors always or write from PL and read from processors. If former, it should always work with no problems except a hardware issue. Run a software memory tester and see if you have reliability issues. If latter, then it could be related to caching. Which AXI port are you using and how are you notifying the processor/cache that the ddr is updated ie cache is invalid?- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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@muzaffer
非常感谢您的留言。 我正在使用zynq-ps将大量数据写入DDR内存。 而且我会说它在99％的情况下有效。 但是我仍然观察到Zynq PS在DDR上写入了一些不正确的数据。 我使用这个函数Xil_DCacheDisable（）; 禁用缓存，我认为缓存在这里没有问题。 现在为了确保写入的数据是正确的，我正在编写并随后读取和比较数据，以确保我的数据是正确的。 但这种方式当然是资源利用不足！ 带着敬意 以上来自于谷歌翻译 以下为原文 @muzaffer Many thanks for your message. I am using zynq-ps to write bulk of data into DDR memory. And I would say it works in 99 percent case. But still I have obserbed that some time some incorrect data is written by Zynq PS on DDR. I am usuing this function Xil_DCacheDisable(); to disable the cache and I think cache is not making a problem here. Now in order to make sure that data is written is correct, i am writing and subsequently reading and comparing the data just to make sure that my data is correct. But this way it is ofcourse underutilization of resourse!. With Regards |
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这应该永远不会发生（即应该在不到10e-13 ber的情况下发生，即你不应该观察它）它发生的事实表明你有一个设计问题。
它可以是软件或硬件。 您可能没有使用配置中的ddr芯片的正确参数。 或者可能是ps ddr实现不正确（阻抗，长度匹配等）或者您的ddr芯片有问题。运行Zynq内存测试程序sdk程序并查看它为您的系统报告的内容。 - 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 That should never happen (ie should happen with less than 10e-13 ber ie you shouldn't be able to observe it) The fact that it happens suggests that you have a design issue. It could be software or hardware. It's possible that you are not using the correct parameters for the ddr chip you have in your configuration. Or it could be that the ps ddr implementation is not proper (impedance, length matching, etc.) or your ddr chip has an issue. Run the Zynq memory tester sdk program and see what it reports for your system. - Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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实际上还有另一种可能性：你有一个糟糕的中断处理程序，它破坏你的处理器的状态，当你接受它时，它会导致你的比较失败。
这不太可能，但可能。 - 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。 以上来自于谷歌翻译 以下为原文 actually there is another possibility: you have a bad interrupt handler which is corrupting your processor's state and when you take it, it causes your compare to fail. It's unlikely but possible.- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. |
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@muzaffer
正如我所说，它并不总是发生，但它确实发生在某个时间（非常罕见）。 而且我也在裸机上看到它，但我还没有使用linux或任何其他操作系统进行测试。 我认为内存测试或任何标准测试可能无法告诉你为什么会发生这种情况！。由于这些测试是内存测试的标准检查，毫无疑问，这在我的设计中运行良好。 目前我没有在设计中使用任何中断。 带着敬意 以上来自于谷歌翻译 以下为原文 @muzaffer As I said you it does not happens always but it does happens sometime(very rarely). And also am seeing it in baremetal, still i have not test using linux or any other OS. I think Memory test or any standard test may not give you clue why this is happening!.As these test are standard check for the memory test and no doubtly this is well functioning in my design. Currently i am not using any interrupt in the design. With Regards |
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