怎么将8位数据和8位地址发送到从属部分以控制照明设备

我可能不应该这样做，但试试这里。
Xilinx文档PG143也可能与您的需求相关。



以下为原文

I probably shouldn't do this, but try here. Xilinx document PG143 may also be relevant to your needs.

None


以下为原文

I am using vivado 2015.3. I imported ise file through vivado and the add constraint file for zybo board as
set_property PACKAGE_PIN L16 [get_ports clk]
set_property IOSTANDARD LVCMOS33[get_ports clk]
set_property PACKAGE_PIN G15 [get_ports updown]
set_property IOSTANDARD LVCMOS33[get_ports updown]
set_property PACKAGE_PIN M14 [get_ports {Q[0]}]
set_property IOSTANDARD LVCMOS33[get_ports {Q[0]}]
set_property PACKAGE_PIN M15 [get_ports {Q[1]}]
set_property IOSTANDARD LVCMOS33[get_ports {Q[1]}]
set_property PACKAGE_PIN G14 [get_ports {Q[2]}]
set_property IOSTANDARD LVCMOS33[get_ports {Q[2]}]
set_property PACKAGE_PIN D18 [get_ports {Q[3]}]
set_property IOSTANDARD LVCMOS33[get_ports {Q[3]}]
set_property PACKAGE_PIN E17 [get_ports reset]
set_property IOSTANDARD LVCMOS33[get_ports reset]
 
At the time of generating bitstream I faced error as
*** Running vivado
    with args -log Count_code.vdi -applog -m64 -messageDb vivado.pb -mode batch -source Count_code.tcl -notrace


****** Vivado v2015.3 (64-bit)
  **** SW Build 1368829 on Mon Sep 28 20:06:43 MDT 2015
  **** IP Build 1367837 on Mon Sep 28 08:56:14 MDT 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source Count_code.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 11 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.3
INFO: [Device 21-403] Loading part xc7z010clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [C:/Users/SAYO/Desktop/pd data/counter/se.xdc]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [C:/Users/SAYO/Desktop/pd data/counter/se.xdc:2]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [C:/Users/SAYO/Desktop/pd data/counter/se.xdc:4]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [C:/Users/SAYO/Desktop/pd data/counter/se.xdc:6]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [C:/Users/SAYO/Desktop/pd data/counter/se.xdc:8]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [C:/Users/SAYO/Desktop/pd data/counter/se.xdc:10]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [C:/Users/SAYO/Desktop/pd data/counter/se.xdc:12]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [C:/Users/SAYO/Desktop/pd data/counter/se.xdc:14]
Finished Parsing XDC File [C:/Users/SAYO/Desktop/pd data/counter/se.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 458.836 ; gain = 244.594
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.541 . Memory (MB): peak = 462.613 ; gain = 3.777
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task
Implement Debug Cores | Checksum: 1a390977d

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1a390977d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 918.602 ; gain = 0.000

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 0 cells.
Phase 2 Constant Propagation | Checksum: 1a390977d

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 918.602 ; gain = 0.000

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 24 unconnected nets.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 3 Sweep | Checksum: 13724b65e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 918.602 ; gain = 0.000

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 918.602 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 13724b65e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 918.602 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 13724b65e

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.352 . Memory (MB): peak = 918.602 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
20 Infos, 0 Warnings, 7 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:33 . Memory (MB): peak = 918.602 ; gain = 459.766
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.371 . Memory (MB): peak = 918.602 ; gain = 0.000
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/SAYO/project_2/project_2.runs/impl_1/Count_code_drc_opted.rpt.
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 918.602 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 918.602 ; gain = 0.000

Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device

Phase 1.1.1 Pre-Place Cells
Phase 1.1.1 Pre-Place Cells | Checksum: 4a824240

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.260 . Memory (MB): peak = 918.602 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 1.1.2 IO and Clk Clean Up
Phase 1.1.2 IO and Clk Clean Up | Checksum: 4a824240

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 1.1.3 Implementation Feasibility check On IDelay
Phase 1.1.3 Implementation Feasibility check On IDelay | Checksum: 4a824240

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 1.1.4 Commit IO Placement
Phase 1.1.4 Commit IO Placement | Checksum: 0b33fe05

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 633c38c1

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 1.2 Build Placer Netlist Model

Phase 1.2.1 Place Init Design
Phase 1.2.1 Place Init Design | Checksum: 8f28e0fa

Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 1.2 Build Placer Netlist Model | Checksum: 8f28e0fa

Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 1.3 Constrain Clocks/Macros

Phase 1.3.1 Constrain Global/Regional Clocks
Phase 1.3.1 Constrain Global/Regional Clocks | Checksum: 8f28e0fa

Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 1.3 Constrain Clocks/Macros | Checksum: 8f28e0fa

Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 1 Placer Initialization | Checksum: 8f28e0fa

Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 2 Global Placement
SimPL: WL = 21664 (1621, 20043)
SimPL: WL = 21187 (1600, 19587)
SimPL: WL = 21242 (1600, 19642)
SimPL: WL = 21002 (1600, 19402)
SimPL: WL = 21151 (1603, 19548)
Phase 2 Global Placement | Checksum: 11d8e7d08

Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 11d8e7d08

Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 173bee37c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1d04fe010

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 3.4 Small Shape Detail Placement

Phase 3.4.1 Commit Small Macros and Core Logic

Phase 3.4.1.1 Commit Slice Clusters
Phase 3.4.1.1 Commit Slice Clusters | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 3.4.1 Commit Small Macros and Core Logic | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 3.4.2 Clock Restriction Legalization for Leaf Columns
Phase 3.4.2 Clock Restriction Legalization for Leaf Columns | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 3.4.3 Clock Restriction Legalization for Non-Clock Pins
Phase 3.4.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 3.4 Small Shape Detail Placement | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 3.5 Re-assign LUT pins
Phase 3.5 Re-assign LUT pins | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 3 Detail Placement | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
Phase 4.1 Post Commit Optimization | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 4.2 Sweep Clock Roots: Post-Placement
Phase 4.2 Sweep Clock Roots: Post-Placement | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 4.3 Post Placement Cleanup
Phase 4.3 Post Placement Cleanup | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 4.4 Placer Reporting
Phase 4.4 Placer Reporting | Checksum: 2549e1cc2

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867

Phase 4.5 Final Placement Cleanup
Phase 4.5 Final Placement Cleanup | Checksum: 230119e64

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 230119e64

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867
Ending Placer Task | Checksum: 13016d670

Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 933.469 ; gain = 14.867
INFO: [Common 17-83] Releasing license: Implementation
33 Infos, 0 Warnings, 7 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 933.469 ; gain = 14.867
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.292 . Memory (MB): peak = 933.469 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.215 . Memory (MB): peak = 933.469 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 933.469 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 933.469 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: fc9b1a12 ConstDB: 0 ShapeSum: 337bbc5e RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1119f8ecf

Time (s): cpu = 00:00:35 ; elapsed = 00:00:33 . Memory (MB): peak = 976.758 ; gain = 43.289

Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.

Phase 2.1 Pre Route Cleanup
Phase 2.1 Pre Route Cleanup | Checksum: 1119f8ecf

Time (s): cpu = 00:00:35 ; elapsed = 00:00:34 . Memory (MB): peak = 982.660 ; gain = 49.191
 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: fff9a529

Time (s): cpu = 00:00:35 ; elapsed = 00:00:34 . Memory (MB): peak = 985.707 ; gain = 52.238

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: b93c34d5

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 985.707 ; gain = 52.238

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
Phase 4.1 Global Iteration 0 | Checksum: ffe3aeac

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 985.707 ; gain = 52.238
Phase 4 Rip-up And Reroute | Checksum: ffe3aeac

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 985.707 ; gain = 52.238

Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: ffe3aeac

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 985.707 ; gain = 52.238

Phase 6 Post Hold Fix
Phase 6 Post Hold Fix | Checksum: ffe3aeac

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 985.707 ; gain = 52.238

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.027027 %
  Global Horizontal Routing Utilization  = 0.00298713 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 10.8108%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 15.3153%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 4.41176%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions.
Phase 7 Route finalize | Checksum: ffe3aeac

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 985.707 ; gain = 52.238

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: ffe3aeac

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 986.480 ; gain = 53.012

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: bbdb18e0

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 986.480 ; gain = 53.012
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:36 ; elapsed = 00:00:34 . Memory (MB): peak = 986.480 ; gain = 53.012

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
41 Infos, 0 Warnings, 7 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:38 ; elapsed = 00:00:36 . Memory (MB): peak = 986.480 ; gain = 53.012
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.283 . Memory (MB): peak = 986.480 ; gain = 0.000
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/SAYO/project_2/project_2.runs/impl_1/Count_code_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
Attempting to get a license for feature 'Implementation' and/or device 'xc7z010'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 7 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Q[3:0], clk, updown, reset.
WARNING: [DRC 23-20] Rule violation (ZPS7-1) PS7 block required - The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
INFO: [Vivado 12-3199] DRC finished with 1 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Wed Apr 13 15:30:51 2016...

你好， 
我发现错误和警告就像我执行UART的verilog代码一样..... plz回复......
错误：HDLCompiler：636  - “C： Users  SAYO  Desktop  pd data  sdses  uart.v”第40行：Net已由输入端口驱动。
警告：HDLCompiler：1499  - “C： Users  SAYO  Desktop  pd data  sdses  uart.v”第21行：空模块仍为黑盒子。
verilog UART代码
`timescale 1ns / 1ps /////////////////////////////////////////////
///////////////////////////////////////公司：//工程师：// //创造
日期：15：15：2016 04/20/2016 //设计名称：//模块名称：uart //项目名称：//目标设备：//工具版本：//说明：////依赖项：//
//修订版：//修订版0.01  - 文件创建//附加注释：//////////////////////////////////
///////////////////////////////////////////// module uart（reset，reset，
txclk，ld_tx_data，tx_data，tx_enable，tx_out，tx_empty，rxclk，uld_rx_data，rx_data，rx_enable，rx_in，rx_empty）; //端口声明输入复位;输入txclk;输入ld_tx_data;输入[7：0] tx_data;输入tx_enable;输出tx_out
;输出tx_empty;输入rxclk;输入uld_rx_data;输出[7：0] rx_data;输入rx_enable;输入rx_in;输出rx_empty;连接rx_in;赋值rx_in = tx_out;
//将接收器连接到发射器互连分配uld_rx_data = ~rx_empty;
//当rx缓冲区已满时卸载数据//内部Variablesreg [7：0] tx_reg; reg tx_empty; reg tx_over_run; reg [3：0] tx_cnt; reg tx_out; reg [7：0] rx_reg; reg [7：0
] rx_data; reg [3：0] rx_sample_cnt; reg [3：0] rx_cnt; reg rx_frame_err; reg rx_over_run; reg rx_empty; reg rx_d1; reg rx_d2; reg rx_busy; always @（posedge rxclk或posedge reset）if（reset）
beginrx_reg rx_data rx_ample_cnt rx_cn rx_empty rx_d1 rx_d2 rx_busy end else begin //同步asynch signalrx_d1 rx_d2 // Uload rx dataif（uld_rx_data）beginrx_data rx_empty end //仅当rx被启用时接收数据if（rx_enable）begin //检查是否只是
收到frameif的开始（！rx_busy＆amp;＆amp;！rx_d2）beginrx_busy rx_sample_cnt rx_cnt endif（rx_busy）beginrx_sample_cnt //在dataif中间采样的逻辑（rx_sample_cnt == 7）beginif（（rx_d2 == 1）＆amp;＆amp;（
rx_cnt == 0））beginrx_busy end else beginrx_cnt //开始存储rx dataif（rx_cnt> 0＆amp;＆amp; rx_cnt rx_reg [rx_cnt  -  1] endif（rx_
cnt == 9）beginrx_busy //检查帧的结束是否正确接收（rx_d2 == 0）beginrx_frame_err end else beginrx_empty rx_frame_err //检查最后的rx数据是否未被卸载，rx_over_run endendendendendendif（！rx_enable）beginrx_busy endendendmodule



以下为原文

hello,
       I found error and warning like when I execute verilog code for UART.....plz reply......
ERROR:HDLCompiler:636 - "C:UsersSAYODesktoppd datasdsesuart.v" Line 40: Net is already driven by input port .
WARNING:HDLCompiler:1499 - "C:UsersSAYODesktoppd datasdsesuart.v" Line 21: Empty module remains a black box.
 
verilog UART code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:    15:15:16 04/20/2016
// Design Name:
// Module Name:    uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
/////////////////////////////////////////////////////////////////////////////
module uart (reset ,txclk ,ld_tx_data ,tx_data ,tx_enable ,tx_out ,tx_empty ,rxclk ,uld_rx_data ,rx_data ,rx_enable ,rx_in ,rx_empty);

// Port declarations
input reset ;
input txclk ;
input ld_tx_data ;
input [7:0] tx_data ;
input tx_enable ;
output tx_out ;
output tx_empty ;
input rxclk ;
input uld_rx_data ;
output [7:0] rx_data ;
input rx_enable ;
input rx_in ;
output rx_empty ;
wire rx_in;

assign rx_in=tx_out ; // connect receiver to transmitter interconnect
assign uld_rx_data =~rx_empty; // unload data when rx buffer is full
// Internal Variables
reg [7:0] tx_reg ;
reg tx_empty ;
reg tx_over_run ;
reg [3:0] tx_cnt ;
reg tx_out ;
reg [7:0] rx_reg ;
reg [7:0] rx_data ;
reg [3:0] rx_sample_cnt ;
reg [3:0] rx_cnt ;
reg rx_frame_err ;
reg rx_over_run ;
reg rx_empty ;
reg rx_d1 ;
reg rx_d2 ;
reg rx_busy ;
always @ (posedge rxclk or posedge reset)
if (reset) begin
rx_reg <= 0;
rx_data <= 0;
rx_sample_cnt <= 0;
rx_cnt <= 0;
rx_frame_err <= 0;
rx_over_run <= 0;
rx_empty <= 1;
rx_d1 <= 1;
rx_d2 <= 1;
rx_busy <= 0;
end else begin
// Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin
rx_data <= rx_reg;
rx_empty <= 1;
end
// Receive data only when rx is enabled
if (rx_enable) begin
// Check if just received start of frame
if (!rx_busy && !rx_d2) begin
rx_busy <= 1;
rx_sample_cnt <= 1;
rx_cnt <= 0;
end
if (rx_busy) begin
rx_sample_cnt <= rx_sample_cnt + 1;
// Logic to sample at middle of data
if (rx_sample_cnt == 7) begin
if ((rx_d2 == 1) && (rx_cnt == 0)) begin
rx_busy <= 0;
end else begin
rx_cnt <= rx_cnt + 1;
// Start storing the rx data
if (rx_cnt > 0 && rx_cnt < 9) begin
rx_reg[rx_cnt - 1] <= rx_d2;
end
if (rx_cnt == 9) begin
rx_busy <= 0;
// Check if End of frame received correctly
if (rx_d2 == 0) begin
rx_frame_err <= 1;
end else begin
rx_empty <= 0;
rx_frame_err <= 0;
// Check if last rx data was not unloaded,
rx_over_run <= (rx_empty) ? 0 : 1;
end
end
end
end
end
end
if (!rx_enable) begin
rx_busy <= 0;
end
end




endmodule