请问为什么第二个周期更长？

1）数据在上升沿产生，但接收器在下降沿采样，我想同时查看dada和接收器时钟。
好像我不能这样做？
源和目标都在FPGA内吗？
如果是这样，你为什么要在时钟的负边缘进行采样 - 这不是正常的同步设计......
但答案是否定的 - 你必须做一些像你正在做的事情 - 对更快的时钟进行过采样。
2）顺便说一下，图表顶部的单位（ms，us，??）是什么？
这就是重点 - 它在SAMPLES中。
逻辑分析仪不是示波器，它不是在连续时间线上采样，而是在采样时钟的边缘采样（你说是100MHz）。
因此，每个样本代表采样时钟的每个连续上升沿上的数据状态。
由于您的时钟是100MHz，每个样本相隔10ns。
3）我可以指示ILA在它找到的下一个边缘触发吗？
是的 - 国际法协会有很多能力。
但ILA的一些功能是在ILA生成时配置的;
要进行边缘触发，您可能需要在生成ILA时配置它（我不是Vivado逻辑分析器/ Chipscope专家）。
Avrum
在原帖中查看解决方案



以下为原文

1) The data is generated on rising edge but the reciever is sampling on falling edge and I wanted to view both the dada and reciever clock at the same time. It seems like as I can't do that?
 
Are the source and destination both inside the FPGA? If so, why would you sample on the negative edge of clocks - that's not normal synchronous design...
 
But the answer is no - you would have to do something like what you are doing - oversampling on a faster clock.
 
2) By the way what is the unit (ms, us, ??) showing on top of the graph?
 
That's the whole point - it is in SAMPLES. A logic analyzer is not an oscilloscope, it is not sampling on a continuous time line, it is sampling on the edges of the sampling clock (which you said was 100MHz). Thus, each sample represents the state of the data on each consecutive rising edge of the sampling clock. Since your clock is 100MHz, each sample is 10ns apart.
 
3) can I instruct the ILA to trigger on next edge that it find?
 
Yes - the ILA has lots of capability. But some of the functionality of the ILA is configured at ILA generation time; to do edge triggering, you may have needed to configure that when you generated the ILA (I am not a Vivado Logic Analyzer / Chipscope expert).
 
Avrum
View solution in original post

弗雷德：看到天空，看到鹅在V形飞行？
你有没有想过为什么V中的一条腿比另一条腿长？
因为长腿中有更多的鹅。
:)
fsahebi2014写道：
你好， 
有人可以告诉我为什么第二个周期更长？
问候，弗雷德
简短回答：因为它是静态采样的大量时钟。
否则，我们需要更多的背景。
***我们中的许多人都是FPGA爱好者，而不是Xilinx员工。
如果您获得帮助并给予荣誉（明星），您将来可能会继续获得帮助。
如果您有解决方案，请将其标记为解决方案。***



以下为原文

Fred: Ever look up into the sky, and see geese flying in a V formation? Did you ever wonder why one of the legs in the V is longer than the other? Because there are more geese in the longer leg. :)

fsahebi2014 wrote:
Hello,
 
  Can someone to tell me why the second cycle is longer? 
 
Regards, Fred

 
Short answer: Because it was sampled a static a larger number of clocks.
Otherwise, we need more context.
***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees.  If you receive help, and give kudos (star), you're likely to continue receiving help in the future.  If you get a solution, please mark it as a solution.***

您必须意识到ILA是一个“内部逻辑分析器”，因此这意味着它使用采样时钟对信号进行数字采样。
您看到的“波形”实际上只是每个连续样本上这些采样值的图。
在这个捕获中，看起来你正在抽样时钟。
因此，在采样时钟的每个上升沿，它将测量采样信号是1还是0.可以说您的采样时钟是采样时钟频率的1/3;
这意味着你应该（平均）得到采样信号为低的1 1/2采样和高采样的1 1/2时钟。
但它是一个逻辑分析仪，所以只能在采样时钟的每个上升沿给你样本 - 它不能显示“1 1/2”样本，它只能显示1或2.所以你会看到每个低
和高时间作为1个样本或2.它们将在足够长的时间内平均到1 1/2，但每个将是1或2。
这可能发生在这里;
你可能试图采样一个稍慢于采样时钟1/2的时钟 - 你看到2个样本高（6503和6504），然后1个样本低（6505），1个高（6506），1个低（
6507），2高（6508和6509）等......
但是，你必须非常小心，你正在采样的这个“时钟”也可能不是观察到的频率;
例如，如果它稍微慢于采样信号的时钟频率的2倍，则可以获得类似的波形 - 再次，您的ILA将在每个采样时钟采样一次信号;
在（例如）6503和6504之间，它可能已经很高（在6503），然后变低然后又回到高点（在6504）并且你将无法分辨。
基于采样和采样时钟的谐波，这看起来仍然是“周期性的” - 这称为“混叠”。
为了确保您没有混叠，您必须采样一个周期信号，其采样率至少是信号频率的2倍 - 更高（并且最好更高）更好。
如果你以100倍采样信号的频率对其进行采样，你仍会看到这种失真，但你的低和高时间只会在50时反弹1次;
即低时间有时是49个样本，有时是50个样本 - 这看起来更像是“时钟”。
Avrum



以下为原文

You have to realize that the ILA is an "Internal Logic Analyzer", so that means that it is digitally sampling signals using a sampling clock. The "waveform" you see is actually just a plot of these sampled values on each successive sample.
 
In this capture, it looks like you are sampling a clock. So, on each rising edge of your sampling clock it is going to measure whether the sampled signal is a 1 or a 0. Lets say your sampled clock is 1/3 the frequency of your sampling clock; this means that you should (on average) get 1 1/2 samples where the sampled signal is low and 1 1/2 clocks where it is high. But it is a logic analyzer so can only give you samples on each rising edge of your sampling clock - it can't show "1 1/2" samples, it can only show 1 or 2. So you will see each of the low and high time either as being 1 sample or 2. They will average out to 1 1/2 over the a long enough period, but each one will be 1 or 2.
 
The same may be happening here; you could be trying to sample a clock that is just slightly slower than 1/2 your sampling clock - you are seeing 2 samples high (6503 and 6504), then 1 sample low (6505), 1 high (6506), 1 low (6507), 2 high (6508 and 6509), etc...
 
However, you have to be REALLY careful here, it is also possible that this "clock" you are sampling is not at all the observed frequency; for example if it were just slightly slower than 2x the clock frequency of the sampling signal, you could get a similar looking waveform - again, your ILA would sample the signal once per sampling clock; between (say) 6503 and 6504, it may have been high (at 6503), then gone low and then gone back high (at 6504) and you won't be able to tell. This would still look "periodic" based on the harmonics of the sampled and sampling clocks - this is called "aliasing".
 
To make sure you are not aliasing, you must sample a periodic signal with a sampling rate at least 2x the frequency of the signal - higher (and preferably much higher) is better. If you were to sample this at 100 times the frequency of the sampled signal, you would still see this distortion, but your low and high time would only bounce around by 1 count on 50; i.e. the low time would sometimes be 49 samples and sometimes 50 samples - this would look much more like a "clock".
 
Avrum

HiAvrum， 
非常感谢您的解释......采样时钟为40MHZ，使用40MHZ时钟但ILA时钟产生的数据设置为100MZ。
一般情况下，您想要对时钟和数据进行采样，ILA的合理CLK是否正确显示？
最好的问候，弗雷德



以下为原文

Hi Avrum,
 
  Thanks so much for your explanation... The sampled clock is 40MHZ, and data generated using 40MHZ clock but ILA clock is set to 100MZ. 
 
In general is you want to sample both clock and data what is the reasonable CLK for ILA to display things correctly?
 
Best regards, Fred

一般情况下，您想要对时钟和数据进行采样，ILA的合理CLK是否正确显示？
不，通常，您希望将ILA用作逻辑分析仪。
逻辑分析仪（主要）用于通过捕获每个周期期间系统的状态来调试同步系统。
因此，如果这是一个简单的同步系统（整个系统在同一时钟上运行），那么使用逻辑分析仪的正常方法是使用系统运行的完全相同的时钟对感兴趣的信号进行采样（和
因此，根本不“抽样”时钟。
因此，逻辑分析仪将在每个连续的时钟周期给出系统状态;
ILA样本6503上的样本将在时钟的上升沿给出系统状态，6504处的样本将在下一个时钟给出系统状态，在6505将给出上升沿的状态
之后的时钟。
因此，如果您的系统以40MHz运行，请使用与您的状态机相同的40MHz时钟作为ILA的采样时钟。
显然，如果你这样做，你就无法对时钟进行采样 - 你将无法在ILA捕获中看到任何时钟信号。
再次，这是正常的 - 时钟是隐含的;
ILA的每个样本代表系统在时钟的连续上升沿上的状态。
Avrum



以下为原文

In general is you want to sample both clock and data what is the reasonable CLK for ILA to display things correctly?
 
No, in general, you want to use the ILA as a logic analyzer. A logic analyzer is (primarily) intended to debug synchronous systems by capturing the state of the system during each cycle. So, if this is a simple synchronous system (the entire system is running on the same clock), then the normal way of using a logic analyzer is to sample the signals of interest using that exact same clock that the system is running on (and, consequently not "sample" the clock at all). Thus, the logic analyzer will give you the state of the system on each successive clock cycle; the sample at ILA sample 6503 will give you the state of the system on that rising edge of clock, the sample at 6504 will give you the state of the system on the next clock, and at 6505 will give you the state on the rising edge of the clock after that.
 
So if your system is running at 40MHz, use the same 40MHz clock that is clocking your state machine as the sampling clock of the ILA.
 
Clearly if you do this, you cannot sample the clock - you will not be able to see any clock signal in your ILA capture. Again, that is normal - the clock is implicit; every sample of the ILA represents the state of the system on a successive rising edge of the clock.
 
Avrum

谢谢 ...
1）数据在上升沿产生，但接收器在下降沿采样，我想同时查看dada和接收器时钟。
好像我不能这样做？
2）顺便说一下，图表顶部的单位（ms，us，??）是什么？
3）我可以指示ILA在它找到的下一个边缘触发吗？



以下为原文

Thanks ...
1) The data is generated on rising edge but the reciever is sampling on falling edge and I wanted to view both the dada and reciever clock at the same time. It seems like as I can't do that?
 
2) By the way what is the unit (ms, us, ??) showing on top of the graph?
 
3) can I instruct the ILA to trigger on next edge that it find?

1）数据在上升沿产生，但接收器在下降沿采样，我想同时查看dada和接收器时钟。
好像我不能这样做？
源和目标都在FPGA内吗？
如果是这样，你为什么要在时钟的负边缘进行采样 - 这不是正常的同步设计......
但答案是否定的 - 你必须做一些像你正在做的事情 - 对更快的时钟进行过采样。
2）顺便说一下，图表顶部的单位（ms，us，??）是什么？
这就是重点 - 它在SAMPLES中。
逻辑分析仪不是示波器，它不是在连续时间线上采样，而是在采样时钟的边缘采样（你说是100MHz）。
因此，每个样本代表采样时钟的每个连续上升沿上的数据状态。
由于您的时钟是100MHz，每个样本相隔10ns。
3）我可以指示ILA在它找到的下一个边缘触发吗？
是的 - 国际法协会有很多能力。
但ILA的一些功能是在ILA生成时配置的;
要进行边缘触发，您可能需要在生成ILA时配置它（我不是Vivado逻辑分析器/ Chipscope专家）。
Avrum



以下为原文

1) The data is generated on rising edge but the reciever is sampling on falling edge and I wanted to view both the dada and reciever clock at the same time. It seems like as I can't do that?
 
Are the source and destination both inside the FPGA? If so, why would you sample on the negative edge of clocks - that's not normal synchronous design...
 
But the answer is no - you would have to do something like what you are doing - oversampling on a faster clock.
 
2) By the way what is the unit (ms, us, ??) showing on top of the graph?
 
That's the whole point - it is in SAMPLES. A logic analyzer is not an oscilloscope, it is not sampling on a continuous time line, it is sampling on the edges of the sampling clock (which you said was 100MHz). Thus, each sample represents the state of the data on each consecutive rising edge of the sampling clock. Since your clock is 100MHz, each sample is 10ns apart.
 
3) can I instruct the ILA to trigger on next edge that it find?
 
Yes - the ILA has lots of capability. But some of the functionality of the ILA is configured at ILA generation time; to do edge triggering, you may have needed to configure that when you generated the ILA (I am not a Vivado Logic Analyzer / Chipscope expert).
 
Avrum