IO无法在低频率下工作，但在更高频率下工作良好

在我们定制的VU440板上，我们对每个银行进行了IO性能测试并发现了一个奇怪的问题，在设计中，我们发送24位伪随机数据并将这些数据循环回到我们的测试板的同一个存储区，其中tx和tx的引脚
rx仅在短路时连接，在设计中将一个差分时钟转换为单端全局时钟，使用IBUFDS + BUFG为tx模块和rx模块提供全局时钟。
但是，我们使用vivado调试工具检查数据循环回来，只发现当时钟在200MHz左右时，数据是正确的，但如果在时钟低得多时无法得到正确的数据，例如10MHz~100MHz。
从我们得到的波形中，我们确定了某个引脚的状态是正常的，因为数据库无法获得正确的数据。
我们找到了有问题的IO引脚，但不知道为什么问题出来了，通常情况下，当频率太高时我们认为IO引脚失效是正常的，但在我们的情况下，问题恰恰相反，我们不明白为什么
它适用于更高的频率，但是当它低得多时却无法运行。
我们现在也尝试检查我们的PCB，但目前还没有任何线索。
有些人有任何想法或建议检查原因吗？
THX〜



以下为原文

On our customized VU440 board, we did a IO performance test for each bank and found a strange problem, in the design,we send out 24bits Pseudo random data and loop back this data to the same bank with our testing board, on which the pins for tx and rx are only connected in short circuit, one differential clock is transfered to single-ended global clock in the design, using IBUFDS+BUFG to provide the global clock for tx module and rx module.

howeve, we use vivado debug tool to check the data looped back, only found when the clock is 200MHz around, the data is correct, but if fails to get correct data when the clock is much lower, for example, 10MHz ~100MHz. And from the waveform we got, we identified the status for some pin was un-normal when the data bus failed to get correct data.
we have found the problematic IO pins, but did not know why the problem come out, normally, we think it's normal for the IO pins fail to work when the frequency is too high, but in our case, the issue is on the contrary, we don't understand why it works for some higher frequency but fail to run when it's much lower.
we now try to check our PCB also, but have no clue at present.
Some guys have any idea or suggestion to check for the reason?
thx~