2
话不多数,直接上代码吧,注释的十分详细了
- /****************************************************/
- /****************************************************/
- /* made by Jerry */
- /****************************************************/
- /****************************************************/
- `timescale 1ns/1ns
- module happy(
- Clk,
- Rst_n,
- SCLK,
- DIN,
- FSY
- );
- //黄正
- input Clk; //系统输入时钟
- input Rst_n; //复位信号
-
- output reg DIN; //AD9833输入数据
- output reg FSY; //数据输入控制信号
- output reg SCLK; //串行通信时钟
- /*
- 串行通信:采用三线SPI(Serial串行 Peripheral外设 Interface接口)形式
- 几个重要的串行接口说明
- SCLK:串行时钟输入,数据在时钟下降沿输入AD9833
- DIN:串行数据输入接口,输入数据位数为16bit
- FSYNC:低有效控制输入Active Low Control Input. This is the frame synchronization signal for the input data. When FSYNC is taken low, the internal logic is informed that a new word is
- being loaded into the device.输入的帧同步信号数据,当FSYNC变低时,会通知内部逻辑一个字节输入完毕。数据只有在FSYNC为低电平时才可以向芯片输入
- 在第16个SCLK下降沿之后FSYNC拉高,
- */
- wire trans_done; //2 byte 数据传输完成标志信号
- reg[3:0]cishu; //字通信次数寄存器,用于控制传输进程
-
- reg[3:0]DIV_CNT; //分频计数器,用于序列机控制
-
- reg SCLK2X; //2倍SCLK的采样时钟
-
- reg [8:0]SCLK_GEN_CNT;//SCLK生成暨序列机计数器
-
- reg en;//转换使能信号
-
- parameter DIV_PARAM=2;
-
- parameter
- DAC_data0=16'h2100, //0010_0001_0000_0000 DB13=1表示即将两次写入完整频率控制字,同时将寄存器复位
- DAC_data1=16'h69f1, //6886 //0110_1001_1111_0001: 低14bit是输入的频率数据,DB15:DB14=01表示选择频率寄存器FEG0
- DAC_data2=16'h4000, // 0100_0000_0000_0000 高14bit=0
-
- DAC_data3=16'hc000, //1100_0000_0000_0000:选择相位寄存器0,data=0
- DAC_data4=16'h0100, // 0000_0001_0000_0000
-
- DAC_data5=16'h2100, //选择数据一次写入,DB13&Rest=1
- DAC_data6=16'h2000, //设置相位寄存器0作为相位累加器
- DAC_data7=16'h2000; //选择正弦波
-
- //数据传输使能控制模块
- always@(posedge Clk or negedge Rst_n)
- if(!Rst_n)
- en <=#1 1'b1;
- else if(trans_done)
- en <=#1 1'b0;
- else
- en <=en;
-
- //完整数据传输完成标志信号
- assign trans_done = (cishu ==4'd8 ) && SCLK2X;
-
- //生成2倍SCLK使时钟计数器
- always@(posedge Clk or negedge Rst_n)
- if(!Rst_n)
- DIV_CNT <= #1 4'd0;
- else if(en)begin
- if(DIV_CNT == (DIV_PARAM - 1'b1))
- DIV_CNT <= #1 4'd0;
- else
- DIV_CNT <= #1 DIV_CNT + 1'b1;
- end else
- DIV_CNT <= #1 4'd0;
- //生成2倍SCLK时钟计数器 结果是使sclk周期为40ns完美
- always@(posedge Clk or negedge Rst_n)
- if(!Rst_n)
- SCLK2X <= #1 1'b0;
- else if(en && (DIV_CNT == (DIV_PARAM - 1'b1)))
- SCLK2X <= #1 1'b1;
- else
- SCLK2X <= #1 1'b0;
-
- //生成序列计数器
- always@(posedge Clk or negedge Rst_n)
- if(!Rst_n)
- SCLK_GEN_CNT <= #1 9'd0;
- else if(SCLK2X && en)
- begin
- if(SCLK_GEN_CNT == 9'd271)
- SCLK_GEN_CNT <= #1 9'd271;
- else
- SCLK_GEN_CNT <= #1 SCLK_GEN_CNT + 1'b1;
- end
- else
- SCLK_GEN_CNT <= #1 SCLK_GEN_CNT;
- /*
- *******************依次将数据移出到芯片********************
- */
- always@(posedge Clk or negedge Rst_n)
- if(!Rst_n)
- begin
- DIN <=#0 1'b1;
- SCLK <=#1 1'b1;
- FSY <=1'b1;
- cishu<=4'd0;
- end
- else if((!trans_done)&&SCLK2X)
- begin
- case(SCLK_GEN_CNT)
- /******************************************************/
- /*传输 DAC_data0*/
- /******************************************************/
- 0:
- begin
- DIN <= #1 DAC_data0[15];
- FSY<=1'b0;
- SCLK <= #5 1'b0;
- end
- 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29:
- begin
- SCLK <= #1 1'b1;
- end
-
- 31:
- begin
- SCLK <= #1 1'b1;
- FSY<= 1'b1;
- end
-
- 2: begin DIN <= #1 DAC_data0[14]; SCLK <= #1 1'b0; end
- 4: begin DIN <= #1 DAC_data0[13]; SCLK <= #1 1'b0; end
- 6: begin DIN <= #1 DAC_data0[12]; SCLK <= #1 1'b0; end
- 8: begin DIN <= #1 DAC_data0[11]; SCLK <= #1 1'b0; end
- 10: begin DIN <= #1 DAC_data0[10]; SCLK <= #1 1'b0; end
- 12: begin DIN <= #1 DAC_data0[9]; SCLK <= #1 1'b0; end
- 14: begin DIN <= #1 DAC_data0[8]; SCLK <= #1 1'b0; end
- 16: begin DIN <= #1 DAC_data0[7]; SCLK <= #1 1'b0; end
- 18: begin DIN <= #1 DAC_data0[6]; SCLK <= #1 1'b0; end
- 20: begin DIN <= #1 DAC_data0[5]; SCLK <= #1 1'b0; end
- 22: begin DIN <= #1 DAC_data0[4]; SCLK <= #1 1'b0; end
- 24: begin DIN <= #1 DAC_data0[3]; SCLK <= #1 1'b0; end
- 26: begin DIN <= #1 DAC_data0[2]; SCLK <= #1 1'b0; end
- 28: begin DIN <= #1 DAC_data0[1]; SCLK <= #1 1'b0; end
- 30: begin DIN <= #1 DAC_data0[0]; SCLK <= #1 1'b0; end
- 32:
- begin
- SCLK <= #1 1'b0;
- end
- 33:
- begin
- SCLK<=1'b1;
- cishu<=4'd1;
- end
- /********************************************************/
- /*传输 DAC_data1*/
- /********************************************************/
- 34:
- begin
- DIN <= #1 DAC_data1[15];
- FSY<=1'b0;
- SCLK <= #5 1'b0;
- end
- 35,37,39,41,43,45,47,49,51,53,55,57,59,61,63:
- begin
- SCLK <= #1 1'b1;
- end
- 65:
- begin
- SCLK <= #1 1'b1;
- FSY<=#1 1'b1;
- end
- 36: begin DIN <= #1 DAC_data1[14]; SCLK <= #1 1'b0; end
- 38: begin DIN <= #1 DAC_data1[13]; SCLK <= #1 1'b0; end
- 40: begin DIN <= #1 DAC_data1[12]; SCLK <= #1 1'b0; end
- 42: begin DIN <= #1 DAC_data1[11]; SCLK <= #1 1'b0; end
- 44: begin DIN <= #1 DAC_data1[10]; SCLK <= #1 1'b0; end
- 46: begin DIN <= #1 DAC_data1[9]; SCLK <= #1 1'b0; end
- 48: begin DIN <= #1 DAC_data1[8]; SCLK <= #1 1'b0; end
- 50: begin DIN <= #1 DAC_data1[7]; SCLK <= #1 1'b0; end
- 52: begin DIN <= #1 DAC_data1[6]; SCLK <= #1 1'b0; end
- 54: begin DIN <= #1 DAC_data1[5]; SCLK <= #1 1'b0; end
- 56: begin DIN <= #1 DAC_data1[4]; SCLK <= #1 1'b0; end
- 58: begin DIN <= #1 DAC_data1[3]; SCLK <= #1 1'b0; end
- 60: begin DIN <= #1 DAC_data1[2]; SCLK <= #1 1'b0; end
- 62: begin DIN <= #1 DAC_data1[1]; SCLK <= #1 1'b0; end
- 64: begin DIN <= #1 DAC_data1[0]; SCLK <= #1 1'b0; end
- 66:
- begin
- SCLK <= #1 1'b0;
- // FSY<=#1 1'b1;
- end
- 67:
- begin
- SCLK<=1'b1;
-
- cishu<=4'd2;
- end
- /***********************************************************/
- /*传输 DAC_data2*/
- /*******************************************************/
- 68:
- begin
- DIN <= #1 DAC_data2[15];
- FSY<=1'b0;
- SCLK <= #5 1'b0;
- end
- 69,71,73,75,77,79,81,83,85,87,89,91,93,95,97:
- begin
- SCLK <= #1 1'b1;
- end
- 99:
- begin
- SCLK <= #1 1'b1;
- FSY<=#1 1'b1;
- end
- 70: begin DIN <= #1 DAC_data2[14]; SCLK <= #1 1'b0; end
- 72: begin DIN <= #1 DAC_data2[13]; SCLK <= #1 1'b0; end
- 74: begin DIN <= #1 DAC_data2[12]; SCLK <= #1 1'b0; end
- 76: begin DIN <= #1 DAC_data2[11]; SCLK <= #1 1'b0; end
- 78: begin DIN <= #1 DAC_data2[10]; SCLK <= #1 1'b0; end
- 80: begin DIN <= #1 DAC_data2[9]; SCLK <= #1 1'b0; end
- 82: begin DIN <= #1 DAC_data2[8]; SCLK <= #1 1'b0; end
- 84: begin DIN <= #1 DAC_data2[7]; SCLK <= #1 1'b0; end
- 86: begin DIN <= #1 DAC_data2[6]; SCLK <= #1 1'b0; end
- 88: begin DIN <= #1 DAC_data2[5]; SCLK <= #1 1'b0; end
- 90: begin DIN <= #1 DAC_data2[4]; SCLK <= #1 1'b0; end
- 92: begin DIN <= #1 DAC_data2[3]; SCLK <= #1 1'b0; end
- 94: begin DIN <= #1 DAC_data2[2]; SCLK <= #1 1'b0; end
- 96: begin DIN <= #1 DAC_data2[1]; SCLK <= #1 1'b0; end
- 98: begin DIN <= #1 DAC_data2[0]; SCLK <= #1 1'b0; end
- 100:
- begin
- SCLK <= #1 1'b0;
- // FSY<=#1 1'b1;
- end
- 101:
- begin
- SCLK<=1'b1;
- // FSY<=#2 1'b1;
- cishu<=4'd3;
- end
- /************************************************************************/
- /*传输 DAC_data3 */
- /************************************************************************/
- 102:
- begin
- DIN <= #1 DAC_data3[15];
- FSY<=1'b0;
- SCLK <= #5 1'b0;
- end
- 103,105,107,109,111,113,115,117,119,121,123,125,127,129,131:
- begin
- SCLK <= #1 1'b1;
- end
- 133:
- begin
- SCLK <= #1 1'b1;
- FSY<=#1 1'b1;
- end
- 104: begin DIN <= #1 DAC_data3[14]; SCLK <= #1 1'b0; end
- 106: begin DIN <= #1 DAC_data3[13]; SCLK <= #1 1'b0; end
- 108: begin DIN <= #1 DAC_data3[12]; SCLK <= #1 1'b0; end
- 110: begin DIN <= #1 DAC_data3[11]; SCLK <= #1 1'b0; end
- 112: begin DIN <= #1 DAC_data3[10]; SCLK <= #1 1'b0; end
- 114: begin DIN <= #1 DAC_data3[9]; SCLK <= #1 1'b0; end
- 116: begin DIN <= #1 DAC_data3[8]; SCLK <= #1 1'b0; end
- 118: begin DIN <= #1 DAC_data3[7]; SCLK <= #1 1'b0; end
- 120: begin DIN <= #1 DAC_data3[6]; SCLK <= #1 1'b0; end
- 122: begin DIN <= #1 DAC_data3[5]; SCLK <= #1 1'b0; end
- 124: begin DIN <= #1 DAC_data3[4]; SCLK <= #1 1'b0; end
- 126: begin DIN <= #1 DAC_data3[3]; SCLK <= #1 1'b0; end
- 128: begin DIN <= #1 DAC_data3[2]; SCLK <= #1 1'b0; end
- 130: begin DIN <= #1 DAC_data3[1]; SCLK <= #1 1'b0; end
- 132: begin DIN <= #1 DAC_data3[0]; SCLK <= #1 1'b0; end
- 134:
- begin
- SCLK <= #1 1'b0;
- // FSY<=#1 1'b1;
- end
- 135:
- begin
- SCLK<=1'b1;
- cishu<=4'd4;
- end
- /************************************************************************/
- /*传输 DAC_data4*/
- /************************************************************************/
- 136:
- begin
- DIN <= #1 DAC_data4[15];
- FSY<=1'b0;
- SCLK <= #5 1'b0;
- end
- 137,139,141,143,145,147,149,151,153,155,157,159,161,163,165:
- begin
- SCLK <= #1 1'b1;
- end
- 167:
- begin
- SCLK <= #1 1'b1;
- FSY<=#1 1'b1;
- end
- 138: begin DIN <= #1 DAC_data4[14]; SCLK <= #1 1'b0; end
- 140: begin DIN <= #1 DAC_data4[13]; SCLK <= #1 1'b0; end
- 142: begin DIN <= #1 DAC_data4[12]; SCLK <= #1 1'b0; end
- 144: begin DIN <= #1 DAC_data4[11]; SCLK <= #1 1'b0; end
- 146: begin DIN <= #1 DAC_data4[10]; SCLK <= #1 1'b0; end
- 148: begin DIN <= #1 DAC_data4[9]; SCLK <= #1 1'b0; end
- 150: begin DIN <= #1 DAC_data4[8]; SCLK <= #1 1'b0; end
- 152: begin DIN <= #1 DAC_data4[7]; SCLK <= #1 1'b0; end
- 154: begin DIN <= #1 DAC_data4[6]; SCLK <= #1 1'b0; end
- 156: begin DIN <= #1 DAC_data4[5]; SCLK <= #1 1'b0; end
- 158: begin DIN <= #1 DAC_data4[4]; SCLK <= #1 1'b0; end
- 160: begin DIN <= #1 DAC_data4[3]; SCLK <= #1 1'b0; end
- 162: begin DIN <= #1 DAC_data4[2]; SCLK <= #1 1'b0; end
- 164: begin DIN <= #1 DAC_data4[1]; SCLK <= #1 1'b0; end
- 166: begin DIN <= #1 DAC_data4[0]; SCLK <= #1 1'b0; end
- 168:
- begin
- SCLK <= #1 1'b0;
-
- end
- 169:
- begin
- SCLK<=1'b1;
- // FSY<=#2 1'b1;
- cishu<=4'd5;
- end
- /************************************************************************/
- /*传输 DAC_data5*/
- /************************************************************************/
- 170:
- begin
- DIN <= #1 DAC_data5[15];
- FSY<=1'b0;
- SCLK <= #5 1'b0;
- end
- 171,173,175,177,179,181,183,185,187,189,191,193,195,197,199:
- begin
- SCLK <= #1 1'b1;
- end
- 201:
- begin
- SCLK <= #1 1'b1;
- FSY<=#1 1'b1;
- end
- 172: begin DIN <= #1 DAC_data5[14]; SCLK <= #1 1'b0; end
- 174: begin DIN <= #1 DAC_data5[13]; SCLK <= #1 1'b0; end
- 176: begin DIN <= #1 DAC_data5[12]; SCLK <= #1 1'b0; end
- 178: begin DIN <= #1 DAC_data5[11]; SCLK <= #1 1'b0; end
- 180: begin DIN <= #1 DAC_data5[10]; SCLK <= #1 1'b0; end
- 182: begin DIN <= #1 DAC_data5[9]; SCLK <= #1 1'b0; end
- 184: begin DIN <= #1 DAC_data5[8]; SCLK <= #1 1'b0; end
- 186: begin DIN <= #1 DAC_data5[7]; SCLK <= #1 1'b0; end
- 188: begin DIN <= #1 DAC_data5[6]; SCLK <= #1 1'b0; end
- 190: begin DIN <= #1 DAC_data5[5]; SCLK <= #1 1'b0; end
- 192: begin DIN <= #1 DAC_data5[4]; SCLK <= #1 1'b0; end
- 194: begin DIN <= #1 DAC_data5[3]; SCLK <= #1 1'b0; end
- 196: begin DIN <= #1 DAC_data5[2]; SCLK <= #1 1'b0; end
- 198: begin DIN <= #1 DAC_data5[1]; SCLK <= #1 1'b0; end
- 200: begin DIN <= #1 DAC_data5[0]; SCLK <= #1 1'b0; end
- 202:
- begin
- SCLK <= #1 1'b0;
-
- end
- 203:
- begin
- SCLK<=1'b1;
- // FSY<=#2 1'b1;
- cishu<=4'd6;
- end
- /************************************************************************/
- /*传输 DAC_data6*/
- /************************************************************************/
- 204:
- begin
- DIN <= #1 DAC_data6[15];
- FSY<=1'b0;
- SCLK <= #5 1'b0;
- end
- 205,207,209,211,213,215,217,219,221,223,225,227,229,231,233:
- begin
- SCLK <= #1 1'b1;
- end
- 235:
- begin
- SCLK <= #1 1'b1;
- FSY<=#1 1'b1;
- end
- 206: begin DIN <= #1 DAC_data6[14]; SCLK <= #1 1'b0; end
- 208: begin DIN <= #1 DAC_data6[13]; SCLK <= #1 1'b0; end
- 210: begin DIN <= #1 DAC_data6[12]; SCLK <= #1 1'b0; end
- 212: begin DIN <= #1 DAC_data6[11]; SCLK <= #1 1'b0; end
- 214: begin DIN <= #1 DAC_data6[10]; SCLK <= #1 1'b0; end
- 216: begin DIN <= #1 DAC_data6[9]; SCLK <= #1 1'b0; end
- 218: begin DIN <= #1 DAC_data6[8]; SCLK <= #1 1'b0; end
- 220: begin DIN <= #1 DAC_data6[7]; SCLK <= #1 1'b0; end
- 222: begin DIN <= #1 DAC_data6[6]; SCLK <= #1 1'b0; end
- 224: begin DIN <= #1 DAC_data6[5]; SCLK <= #1 1'b0; end
- 226: begin DIN <= #1 DAC_data6[4]; SCLK <= #1 1'b0; end
- 228: begin DIN <= #1 DAC_data6[3]; SCLK <= #1 1'b0; end
- 230: begin DIN <= #1 DAC_data6[2]; SCLK <= #1 1'b0; end
- 232: begin DIN <= #1 DAC_data6[1]; SCLK <= #1 1'b0; end
- 234: begin DIN <= #1 DAC_data6[0]; SCLK <= #1 1'b0; end
- 236:
- begin
- SCLK <= #1 1'b0;
- // FSY<=#1 1'b1;
- end
- 237:
- begin
- SCLK<=1'b1;
- cishu<=4'd7;
- end
- /************************************************************************/
- /*传输 DAC_data7*/
- /************************************************************************/
- 238:
- begin
- DIN <= #1 DAC_data7[15];
- SCLK <= #5 1'b0;
- FSY<=1'b0;
- end
- 239,241,243,245,247,249,251,253,255,257,259,261,263,265,267:
- begin
- SCLK <= #1 1'b1;
- end
- 269:
- begin
- SCLK <= #1 1'b1;
- FSY<=#1 1'b1;
- end
- 240: begin DIN <= #1 DAC_data7[14]; SCLK <= #1 1'b0; end
- 242: begin DIN <= #1 DAC_data7[13]; SCLK <= #1 1'b0; end
- 244: begin DIN <= #1 DAC_data7[12]; SCLK <= #1 1'b0; end
- 246: begin DIN <= #1 DAC_data7[11]; SCLK <= #1 1'b0; end
- 248: begin DIN <= #1 DAC_data7[10]; SCLK <= #1 1'b0; end
- 250: begin DIN <= #1 DAC_data7[9]; SCLK <= #1 1'b0; end
- 252: begin DIN <= #1 DAC_data7[8]; SCLK <= #1 1'b0; end
- 254: begin DIN <= #1 DAC_data7[7]; SCLK <= #1 1'b0; end
- 256: begin DIN <= #1 DAC_data7[6]; SCLK <= #1 1'b0; end
- 258: begin DIN <= #1 DAC_data7[5]; SCLK <= #1 1'b0; end
- 260: begin DIN <= #1 DAC_data7[4]; SCLK <= #1 1'b0; end
- 262: begin DIN <= #1 DAC_data7[3]; SCLK <= #1 1'b0; end
- 264: begin DIN <= #1 DAC_data7[2]; SCLK <= #1 1'b0; end
- 266: begin DIN <= #1 DAC_data7[1]; SCLK <= #1 1'b0; end
- 268: begin DIN <= #1 DAC_data7[0]; SCLK <= #1 1'b0; end
- 270:
- begin
- SCLK <= #1 1'b0;
- // FSY<=#1 1'b1;
- end
- 271:
- begin
- SCLK<=1'b1;
- cishu<=4'd8;
- end
- default:;
- endcase
- end
- endmodule
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我写了一个tb文件进行模拟仿真测试,测试代码:
- /****************************************************/
- /****************************************************/
- /* made by Jerry */
- /****************************************************/
- /****************************************************/
- `timescale 1ns/1ns
- `define clock_period 20
- module happy_tb;
- reg Clk;
- reg Rst_n;
-
- wire DIN; //传输bit
- wire FSY; //数据输入标志信号
- wire SCLK; //通信时钟
- // wire [3:0]cishu;
- //wire en;
-
- happy happy(
- .Clk(Clk),
- .Rst_n(Rst_n),
- .SCLK(SCLK),
- .DIN(DIN),
- .FSY(FSY)
- // .cishu(cishu)
- );
-
- initial Clk = 1;
- always#(`clock_period/2) Clk=~Clk;
-
- initial begin
- #200;
- Rst_n=1'b0;
- #200;
- Rst_n=1'b1;
- #200000;
- #200;
- Rst_n=1'b0;
- #200;
- Rst_n=1'b1;
- #200000;
- #200;
- Rst_n=1'b0;
- #200;
- Rst_n=1'b1;
- #200000;
- #200;
- Rst_n=1'b0;
- #200;
- Rst_n=1'b1;
- #200000;
- #200000;
- #200;
- Rst_n=1'b0;
- #200;
- Rst_n=1'b1;
- #200000;
- $stop;
- end
- endmodule
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