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嗨,我在PIC16F1824中读取波特率发生器部分,用于编码I2C通信程序……我附加了三张我不理解的图片。在图1中,当SSP1BUF发生写入时,波特率发生器将自动开始计数。不管是在接收机模式还是在发射机模式中,它的值都投入到SSP1BUF中去了?(我猜是)在BGR计数器重新装入之前,BGR计数器的初始值是多少?一旦给定的操作完成,内部时钟将自动停止计数,时钟引脚将保持在其最后状态。“内部时钟”的时钟BRG的计数器?“时钟引脚”的SCL引脚?图24至39中的内部信号“重新装入”触发SSP1ADD的值,以加载到BRG计数器中,图24至39中的内部信号“重新加载”在哪里?(图片2)对于模块时钟线每次发生两次振荡,这两次发生两次?“重装动作”?模块时钟线的每一个振荡表示SCL中的时钟周期?当重新加载信号被断言时,逻辑指令取决于MSSP1正在运行的模式。据我所知,MSSP1寄存器决定主模式中的SPCL引脚时钟周期,但如何知道MSSP1寄存器中的“何时重新加载信号”?表244演示了基于指令周期的时钟速率和加载到SSP1ADD.W/BRG&LT中的BRG值:“W”表示什么?FCY是什么?指令周期的频率?什么是FCLOCK(2翻滚BRG)?我完全不明白。对不起,每次都需要这么多的问题,我读的很辛苦,但还是不明白。
以上来自于百度翻译 以下为原文 Hi, I've been reading the BAUD RATE GENERATOR section in PIC16F1824 for coding a I2C communication program...... I attached the three pictures where I don't understand. In picture 1 When a write occurs to SSP1BUF, the Baud Rate Generator will automatically begin counting down. "a write" in here indicate the value put into the SSP1BUF no matter in receiver mode or transmitter mode?(I guessed yes) What is the initial value in BGR's counter before BGR's counter is reloaded? Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. Is "internal clock" the clock of BRG's counter? Is "clock pin" the SCL pin? An internal signal “Reload” in Figure 24-39 triggers the value from SSP1ADD to be loaded into the BRG counter Where is the internal signal "Reload" in Figure 24-39?(picture 2) This occurs twice for each oscillation of the module clock line What occurs twice? the "action of reload"? "Each oscillation of the module clock line" indicates a clock period in SCL? The logic dictating when the reload signal is asserted depends on the mode the MSSP1 is being operated in. As far as I know, the MSSP1 register decide the SCL pin clock period in Master mode, but how do I know "when the reload signal is asserted" from MSSP1 register? Table 24-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSP1ADD. W/BRG <-- What "W" indicates? What is FCY? frequency of instruction cycle? What is FCLOCK(2 Rollovers of BRG)? I totally don't understand it. Sorry, require so many questions at a time, I read it very hard but still don't understand..... Attached Image(s) |
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我假设你说的是I2C,就像你最后的ththHTTP://www. McCHIP.COM/FUMMS/M99 4212.ASPX所指出的,在谈论“发送器”或“接收器”方面没有多大意义,而不是主人或奴隶。
以上来自于百度翻译 以下为原文 I assume you're talking I2C, as per your last thread http://www.microchip.com/forums/m994212.aspx Just to note that there's not much sense in talking about "transmitter" or "receiver", rather Master or Slave. |
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…为什么你有这么多的话题都在谈论BRG发生器?把所有的讨论都放在一个题目中要容易得多。
以上来自于百度翻译 以下为原文 ... and why do you have so many topics active all talking about the BRG generator? It's much easier to keep all the discussion in ONE topic. |
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Yes不要紧,它是不是,这个图表正在讨论其他的事情,关于总线碰撞而不是BGR重新加载,在SCL时钟的每一个半周期中,一次是低的,一次是高水平的,一个低的和一个高的周期,你为什么关心?MSSP模块在内部执行此操作。“BRG”周期的指令时钟时钟的速记是得到的SCL时钟频率,该时钟的每个半周期由BRG计数器的一个“翻转”来定义。R“翻转”在这里意味着计数器计数它被“重载”的次数。
以上来自于百度翻译 以下为原文 Yes Does not matter, probaby zero Yes Yes It isn't, that diagram is discussing something else, about bus collisions not BGR reload Yes, on each half-cycle of the SCL clock-once for LOW and once for HIGH level Yes, one LOW and one HIGH period Why do you care? The MSSP module does this internally. Shorthand for "with BRG" Cycle time of the instruction clock FCLOCK is the resultant SCL clock frequency, each half period of this clock is defined by one "rollover" of the BRG counter. R "rollover" here means the counter counts the number of times it was "reloaded" with. |
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安迪,你对这个问题的了解太多了。这是在问PIC内部如何添加两个值,你不需要知道仅仅使用它。你的大多数问题与使用I2C外围设备无关。
以上来自于百度翻译 以下为原文 Andy, you really are going into this in too much detail. This is on the level of asking how the PIC internally adds two values, you don't need to know to just use it. Most of your questions have no relevance to simply using the I2C peripheral. |
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