什么是转换22位输入相当于8位输出的逻辑

不确定你的意思。
你需要截断14位来转换8位。
对于inout，您可以使用8位作为输入，另外8位作为输出。
你仍然有6位截断。
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

not sure what you meant . you need to truncate 14 bits to convert 8 bits.

For inout you can use 8 bits as input and  another 8 bits as output. You still have 6 bits for truncate.Thanks and Regards
Balkrishan
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嗨，
这是我的代码。
在这个我不同的时间段和总时间段。
现在的问题是锁定时间段。
当我将改变总时间段时如何在此代码中添加此限定。
我是vhdl的初学者。
我也在使用22输入来改变总时间段，我们可以将其减少8。
library IEEE;使用IEEE.std_logic_1164.all;
使用IEEE.numeric_std.all;使用ieee.std_logic_unsigned.all;
- 对于无符号类型
实体计数器是通用的（counter_width：integer：= 22）;
port（clk，rst：in std_logic; duty：in std_logic_vector（counter_width-1 downto 0）; period：in std_logic_vector（counter_width-1 downto 0）; pwm：out std_logic）; end entity counter;
架构counter_arch of counter开始更新：process（clk，rst）变量count：std_logic_vector（counter_width-1 downto 0）;
如果（rst ='1'）则开始计数：=“0000000000000000000000”;
pwm elsif（clk'event和clk ='1'）然后计数：= count + 1;
if（count = duty）然后pwm结束if;
if（count = period）then count：=“0000000000000000000000”;
pwm结束如果;
万一;
结束过程;
结构体系结构counter_arch;



以下为原文

Hi,
This is my code . in this i am varying on time period and total time period. now problem is latch on time time period. when i will vary total time period.how to add this secification in this code. I am beginner in vhdl. I also A s i am using 22 input to vary the total time period how we able reduce it by 8.
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all; -- for the unsigned type
entity counter is
generic(counter_width: integer:=22);
port (clk,rst : in std_logic;
duty :in std_logic_vector(counter_width-1 downto 0);
period:in std_logic_vector(counter_width-1 downto 0);
pwm : out std_logic);
end entity counter;
architecture counter_arch of counter is
begin
update: process(clk,rst)
variable count : std_logic_vector(counter_width-1 downto 0);
begin
if(rst='1')then
count:= "0000000000000000000000";
pwm <= '1';
elsif(clk'event and clk ='1')then
count:= count + 1;
if(count = duty)then
pwm <='0';
end if;
if(count = period)then
count:= "0000000000000000000000";
pwm <='1';
end if;
end if;
end process;

end architecture counter_arch;
 

shriam_nerkar1写道：
嗨，
这是我的代码。
library IEEE;使用IEEE.std_logic_1164.all;
使用IEEE.numeric_std.all;使用ieee.std_logic_unsigned.all;
- 对于无符号类型
没有。
numeric_std库包含无符号类型。
永远不需要使用std_logic_unsigned库。
----------------------------是的，我这样做是为了谋生。



以下为原文

shriam_nerkar1 wrote:
Hi,
This is my code .
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all; -- for the unsigned type 

NO. 
 
The numeric_std library includes the unsigned type. There is never a need to use the std_logic_unsigned library.
----------------------------Yes, I do this for a living.