Synopsys无法对Xilinxlibrary xilinxcorelib进行重新命名

>或者我唯一可以获得ASIC芯片布局的是编写没有Xilinx内核生成器组件的纯VHDL代码
正如其他人指出的那样，System Generator创建了专门针对Xilinx原语，单元和特征的网表。
此外，您在安装该工具时接受的软件许可证特别限制了Xilinx产品的使用，因此将代码和移植到其他技术的行为违反了许可协议。
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在原帖中查看解决方案



以下为原文

> Or the only we I can get the ASIC silicon layout is to write a pure VHDL code without Xilinx core generator components
 
As other have pointed out the System Generator creates netlists that are specifically target to Xilinx primitives, cells and features.  In addition the software license that you accept when you installed the tool specifically restrictives the usage to Xilinx products, so taking the code and porting it to another technology is in violation of the licensing agreement.
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我认为Synopsys目前不支持Xilinx Designs的工具
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

I think Synopsys is not supported tool for Xilinx Designs for nowThanks and Regards
Balkrishan
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嗨，
由sysgen生成的代码将具有基于FPGA的预发布。
如果您尝试将其映射为使用ASIC工具进行综合，则显然会出现错误。
这是因为ASIC工具搜索基于FPGA的代码的预先定义。
如果您想将基于FPGA的代码运行到ASIC流程，那么您需要使用ASIC技术库重新映射基于FPGA的预发布。
问候，
KR
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Hi,
 
The code generated out of sysgen will have FPGA based premitives.
If you try to map this to synthesize this with a ASIC tool it will obviously errorout.

This is because the ASIC tool searches for the premitive definition of of FPGA based code.
 
If you want to run the FPGA based code to ASIC flow , then you need to remap the FPGA based premitives with the ones of ASIC technology library.
 
Regards,
KR
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>或者我唯一可以获得ASIC芯片布局的是编写没有Xilinx内核生成器组件的纯VHDL代码
正如其他人指出的那样，System Generator创建了专门针对Xilinx原语，单元和特征的网表。
此外，您在安装该工具时接受的软件许可证特别限制了Xilinx产品的使用，因此将代码和移植到其他技术的行为违反了许可协议。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> Or the only we I can get the ASIC silicon layout is to write a pure VHDL code without Xilinx core generator components
 
As other have pointed out the System Generator creates netlists that are specifically target to Xilinx primitives, cells and features.  In addition the software license that you accept when you installed the tool specifically restrictives the usage to Xilinx products, so taking the code and porting it to another technology is in violation of the licensing agreement.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com