是否必须更改微填充Icache的地址区域

处理器缓存通常不是直接映射的，这是您所描述的。
它们具有某种所谓的“缓存关联性”，它基本上可以将缓存划分为小部分，并且基于访问哪些地址，每个部分可以缓存较大存储器的某个区域（在这种情况下为dram）。
当然，关联性有其自身的成本（主要是硬件和缓存延迟），因此不会使缓存完全关联（即每个字都可以指向不同的dram地址）。
在MB中，可以在生成期间设置缓存关联性。
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以下为原文

Processor caches are usually not direct mapped which is what you are describing. They have a certain what's termed "cache associativity" which basically can divide the cache into small sections and based on which addresses are accessed each section can cache a certain region of the larger memory (dram in this case). Of course associativity has its own cost (mainly hardware and cache latency) so one doesn't make a cache fully associative (ie every word can point to a different dram address). In MB, cache associativity can be set during generation.- Please mark the Answer as "Accept as solution" if information provided is helpful.
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那么，数据缓存基地址和高地址只是表明什么是可缓存地址？
在配置微纤维时，可以选择在哪里更改缓存的关联性？
我没看到。
而且默认情况下，关联性和集合方面的缓存参数是什么？



以下为原文

So, the data cache base address and high address just indicate what is the cacheable address? And where is the option to change the associativity of the cache when configuring the microblaze? I do not see it. And also by default what are the cache parameters in terms of associativity and sets?

你好
有关缓存组织的信息，请参见http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf的第63页。
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以下为原文

Hi
 
The cache organization is mentioned in page 63 of http://www.xilinx.com/support/documentation/sw_manuals/mb_ref_guide.pdf
 
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是基地址和高地址表示可缓存区域。
关于关联性：事实证明MB缓存是单向的，即直接映射，因此它们没有关联性配置。
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以下为原文

Yes base address and high address indicate the cacheable region. About associativity: it turns out the MB caches are 1-way ie direct mapped, so there is no associativity configuration for them.- Please mark the Answer as "Accept as solution" if information provided is helpful.
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