FPGA初始化时间延迟怎么减少

嗨，
这通常是配置时间。
配置所需的时间在本文档的第19页中给出
有关更多详细信息，请参阅此论坛帖子。
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-configuration-times/td-p/193896
--HS
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以下为原文

Hi,
 
This is usually the configuration time. The time taken for configuration is given in page 19 of this doc
 
Refer to this forum post for more detailed information. 
 
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-configuration-times/td-p/193896
 
--HS
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要添加已有的良好信息，可以在创建配置文件时在bitgen选项中设置CCLK频率。
您可以使用的最大频率取决于外部设备（通常是SPI闪存）。
大多数现代SPI闪存部件都可以处理最高可用频率，但您需要检查数据表以确定。
另请参阅Spartan 6数据表了解CCLK频率容差。
请注意，它非常大（类似于+/- 50％IIRC），在决定SPI闪存可以处理的频率时，必须考虑到这一点。
-  Gabor



以下为原文

To add to the good information you already have, the CCLK frequency can be set in the bitgen options when you create the configuration file.  The maximum frequency you can use will depend on the external device (usually a SPI flash).  Most modern SPI flash parts can handle the highest available frequencies, but you need to check the data sheet to be sure.  Also look at the Spartan 6 datasheet for the CCLK frequency tolerance.  Note that it is quite large (something like +/- 50% IIRC) and you must take this into account when deciding what frequency your SPI flash can handle.
-- Gabor

嗨，
如果您找到了查询的解决方案，请标记答案。
这是JTAG还是SPI，BPI配置？
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
Please mark the answer in case you found the solution to your query.
 
Is this with the JTAG or the SPI, BPI configuration?
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

这个时间是有一些长了，可以看一下你的时钟是怎么配置的