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IDK发生了什么......昨天我成功完成了综合...我没有改变任何事情......今天我无法完成综合......
它陷入了这个阶段： 以上来自于谷歌翻译 以下为原文 IDK what's happening... Yesterday I succeeded in the completion of synthesis... I didn't change anyhting... and today I'm not able to complete the synthesis.... It's stuck in this phase: 
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9个回答
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如果没有改变，你为什么要重新合成设计呢？
------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 If nothing changed, why did you resynthesize the design? ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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我做了......一百次......而且所有的时间都停留在同一个地方......状态|
编码-------------------------- s_init | 00 s_payload | 10 s_sendheader | 11 s_header | 01 以上来自于谷歌翻译 以下为原文 I did... a hundred times... and all the time stucks at the same place.... State | Encoding -------------------------- s_init | 00 s_payload | 10 s_sendheader | 11 s_header | 01 |
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在您的原始帖子中，您说没有任何改变，但当您重新合成时，它会挂起。
如果没有改变，则不需要重新运行合成，因此看起来实际上已经发生了变化。 如果您无法提供更多详细信息，论坛将无法提供帮助。 ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 In your original post you said that nothing changed, but when you reran synthesis it hung. Rerunning synthesis would not be required if nothing changed, so it would seem that something in fact has changed. If you can't provide more details the forums won't be able to help.------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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我在testbench文件上改了一些东西，但后来我改回来......然后他说我的综合已经过时了，所以我重新合成了这个项目，并且它被困在那个地方。
我之前做过的一件事可能会导致一些错误..我安装了Modelsim来运行模拟，但我无法运行它，因为它说我的Unisim版本与ISE不同......类似的东西...... 。 以上来自于谷歌翻译 以下为原文 I changed something on the testbench file, but later I changed back... and then he said my synthesis was out of date, so I resynthetized the project, and it's stucked in that place. One thing that i had done before that maybe caused some bug.. I installed the Modelsim to run the simulation, but i was not able to run it because it said my version of Unisim was different from ISE... something like that... |
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它可以是任何合成设置吗？
也许我已经改变了......最好的设置是什么？ 以上来自于谷歌翻译 以下为原文 Can It be any synthesis setting? Maybe I have changed it... What's the best setting? |
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虽然您继续说您的代码没有任何变化，但这是解释行为差异的唯一合理解释。
有时，由于格式错误的生成或for循环，它可能会产生大量的逻辑，导致合成器在极长的时间内工作。 我建议您合成每个模块个体，看看哪个模块有问题。 ------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 While you continue to say that nothing changed in your code, that is the only logical explanation to explain the difference in behavior. Sometimes with badly formed generate or for loops it can create an huge amount of logic that will cause the synthesizer to work for extreme lengths of time. I would suggest that you synthesis each module individual to see which one is at fault. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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我改变了一些东西，但它是在测试平台上，对合成没有兴趣......
以上来自于谷歌翻译 以下为原文 I've changed things, but it was on the testbench, that doesn't interest on the synthesis... |
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由于该计划坚持这一部分：
--------------------------状态| 编码-------------------------- s_init | 00 s_payload | 10 s_sendheader | 11 s_header | 01 -------------------------- 我试图看到包含s_init，s_payload指令的文件......它在附件上。 Hermes_buffer.vhd 11 KB 以上来自于谷歌翻译 以下为原文 Since the program stucks on this part: -------------------------- State | Encoding -------------------------- s_init | 00 s_payload | 10 s_sendheader | 11 s_header | 01 -------------------------- I tried to see the file that contains the instruction of s_init, s_payload ... It's on the attachment. |
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在状态编码上打印的信息可能是成功处理的最后一个好部分，而不是挂起发生的地方。
------您是否尝试在Google中输入问题？ 如果没有，你应该在发布之前。太多结果？ 尝试添加网站：www.xilinx.com 以上来自于谷歌翻译 以下为原文 The information that was printed on the state encoding is likely the last good part that was processed sucessfully and not where the hang is occurring. ------Have you tried typing your question into Google? If not you should before posting. Too many results? Try adding site:www.xilinx.com |
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