怎么为8位系统创建2的补码转换器

你好
您可以通过反转输入并将1加1来实现2的补码。
如果你做一个简单的谷歌搜索，你会发现很多关于这方面的例子。
请查看以下链接以获取简单的代码
http://www.vlsibank.com/sessionspage.asp?titl_id=34952
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
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在原帖中查看解决方案



以下为原文

Hi
 
You can implement 2's complement simple by inverting the input and adding 1 to it.
 
you will find lot of examples about that if you do a simple google search.
 
Look at below link for a simple code for this
 
http://www.vlsibank.com/sessionspage.asp?titl_id=34952
Regards,

Satish

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Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------View solution in original post

你好
您可以通过反转输入并将1加1来实现2的补码。
如果你做一个简单的谷歌搜索，你会发现很多关于这方面的例子。
请查看以下链接以获取简单的代码
http://www.vlsibank.com/sessionspage.asp?titl_id=34952
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
You can implement 2's complement simple by inverting the input and adding 1 to it.
 
you will find lot of examples about that if you do a simple google search.
 
Look at below link for a simple code for this
 
http://www.vlsibank.com/sessionspage.asp?titl_id=34952
Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

十分感谢你的帮助！
我很高兴学习如何更好地使用这个程序。
我做了你的建议并用谷歌搜索了这个问题，看看我能完成同样任务的其他方法（出于好奇）。
每个解决方案都使用该行：
“DOUT
但是，出于某种原因，我不断收到错误“+在此上下文中无法进行此类操作”。
它引用了我上面发布的代码行。
我在网上环顾四周，但似乎没有人遇到同样的错误。
知道为什么会发生这种情况吗？
- 安东尼



以下为原文

Thank you so much for the help!
 
I am very excited about learning how to use this program better.  I did what you suggested and googled this problem to see other ways I could finish the same task (out of curiosity).  Every solution used the line:
 
"dout <= not(din) + "00000001";"



However, for some reason I keep getting the error  "+ can not have such operations in this context."  And it cites the line of code I posted above.  I looked around online but no one seems to be having the same error I am having.  Any idea why this could be happeneing?
 
-Anthony

你好
当代码中未包含定义信号类型的运算符的包时，您将收到这些错误。
http://forums.xilinx.com/t5/General-Technical-Discussion/strange-VHDL-Testbench-error/td-p/182048
作为一种语言的新用户，学习的方法是查看标准语言参考手册，了解它
基本语言结构。
尝试使用简单的示例来熟悉该语言。
问候，萨蒂什-----------------------------------------------
--- --------------------------------------------请注意
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用的帖子。感谢.--
---------------------------- ---------------------
----------------------



以下为原文

Hi
 
You will get these errors when packages which define the operators for the signal types are not included in your code.
 
http://forums.xilinx.com/t5/General-Technical-Discussion/strange-VHDL-Testbench-error/td-p/182048
 
As a new user of a language the way to learn is to look into a standard language reference manual understanding the
basic language constructs.
 
Trying out simple example's to get familiar with the language.
 
Regards,

Satish

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------

我在你发布的链接上找到了修复程序！
非常感谢你再次帮助我：]
对于其他任何看到这个并且遇到同样问题的人，我所要做的就是添加以下库以使“+”工作。
库ieee;使用ieee.std_logic_1164.all;使用ieee.std_logic_arith.all;使用ieee.std_logic_textio.all;使用ieee.numeric_std.all;使用IEEE.std_logic_unsigned.all;



以下为原文

I found the fix on the link you posted! Thank you so much for helping me again :]
 
For anyone else looking at this and having the same problem, all I had to do was add the below libraries in order to let the "+" work.
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_textio.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
 

anthony57写道：
十分感谢你的帮助！
我很高兴学习如何更好地使用这个程序。
我做了你的建议并用谷歌搜索了这个问题，看看我能完成同样任务的其他方法（出于好奇）。
每个解决方案都使用该行：
“DOUT
但是，出于某种原因，我不断收到错误“+在此上下文中无法进行此类操作”。
它引用了我上面发布的代码行。
我在网上环顾四周，但似乎没有人遇到同样的错误。
知道为什么会发生这种情况吗？
- 安东尼
那是因为您可能将信号din和dout声明为std_logic_vector，并且没有为这些类型定义数学运算。
你真的需要使用numeric_std库（不要使用STD_LOGIC_ARITH和STD_LOGIC_UNSIGNED）并将dout声明为signed（7 downto 0）并将din声明为unsigned（7 downto 0）。
然后，管理类型转换很简单：
dout / std_logic_unsigned，因为这些库不允许您在同一实体中混合使用std_logic_vectors的有符号和无符号解释。
在赋值示例中，您正在使用std_logic_unsigned库，这意味着对于数学运算，假设您的信号dout是无符号的。
然而，操作显然是将无符号值转换为2的补码等价值。
这显然是造成很大混乱的原因。
创建了numeric_std库及其signed和unsigned类型来解决这个问题。
----------------------------是的，我这样做是为了谋生。



以下为原文

anthony57 wrote:
Thank you so much for the help!
 
I am very excited about learning how to use this program better.  I did what you suggested and googled this problem to see other ways I could finish the same task (out of curiosity).  Every solution used the line:
 
"dout <= not(din) + "00000001";"



However, for some reason I keep getting the error  "+ can not have such operations in this context."  And it cites the line of code I posted above.  I looked around online but no one seems to be having the same error I am having.  Any idea why this could be happeneing?
 
-Anthony

That's because you likely have the signals din and dout declared as std_logic_vector, and math operations are not defined for those types. You really need to use the numeric_std library (DO NOT EVER USE STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED) and declare dout as signed(7 downto 0) and din as unsigned(7 downto 0).
 
Then it's a simple matter of managing the type conversions:
 
dout <= signed(not(din) + 1);
 
PS: so this sort of thing is the reason why you shouldn't use std_logic_arith/std_logic_unsigned, because those libraries won't let you mix signed and unsigned interpretations of std_logic_vectors in the same entity. In your assignment example, you're use-ing the std_logic_unsigned library, which means that for math operations, your signal dout is assumed to be unsigned. Yet the operation is explictly to convert an unsigned value to its 2's complement signed equivalent. That's obviously a cause for great confusion.
 
The numeric_std library and its signed and unsigned types were created to solve this very problem. 
----------------------------Yes, I do this for a living.

非常感谢你的投入！
我最终摆脱了这些库，并使用unsigned来使其工作。
很高兴知道我不应该使用它们。
到目前为止，我在语法和学习功能方面遇到了很多麻烦。
我相信你将来会收到我的消息！
到目前为止，我很喜欢这个节目。
对于将来可能有任何问题的任何人，我最终用来让我的工作的代码是：
库ieee;使用ieee.std_logic_1164.all;使用ieee.numeric_std.all;实体twoscomp isport（din：在std_logic_vector（7 downto 0）; dout：out std_logic_vector（7 downto 0））; end twoscomp; architecture行为twoscomp i***egindout
结束行为;



以下为原文

Thank you so much for that input!  I ended up getting rid of those libraries and using unsigned instead to get it to work.  Good to know that I shouldn't use those.  So far I've just been having a lot of trouble with syntax and learning what functions are at my disposal.  I'm sure you will hear from me in the future!
 
So far I am loving this program.  For anyone who may have any questions in the future, the code I ended up using to get mine to work was:
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity twoscomp is
port( din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0));
end twoscomp;

architecture Behavioral of twoscomp is

begin

dout <= std_logic_vector (unsigned(not din) + 1);
end Behavioral;