如何提高DMA的效率？

嗨，
DMA意味着直接内存访问是特定于应用程序
通常，您有一个处理器和一些（可编程）DMA控制器，可在处理器RAM和某些目标之间移动数据。
以前经常是一些大容量存储设备，有时也是图形设备。
Xilinx具有多通道内存控制器IP，这是某些支持DMA的架构的关键元素。
主要问题是存储器I / O带宽与CPU最大访问速度之间是否存在差距。
如果是这样，这个间隙可用于DMA访问而不会降低CPU的速度。
如果为每个通道添加由BRAM制作的小缓存，则可能会增加多通道DMA的性能。
但是，实际实现取决于您的设计要求以及您将要使用的器件（FPGA和RAM）的功能。
根据您的要求提出所有数字，并寻找合适的设备。
还要记住，FPGA可以独立驱动多个存储体。
__________________
这个双向的事情怎么样？
通常，DMA是单向的，因为在查看单个通道时，您希望将数据移入OR内存中。
如果你有单独的读写通道，除非内存带宽足够，否则这没有问题。
再想想多个存储库。
请记住，任何风格的DRAM（SD，DDR（2/3），QDR）在块访问（称为突发模式）上表现最佳。
因此，您将读取一大块数据，然后写入另一个块。
你可以一次在同一个地址上做两件事，但我怀疑这是你想要的。
有一个很好的综合 
Eilert



以下为原文

Hi,
DMA meaning Direct Memory Access is application specific.
Normally you have a processor and some (programmable) DMA controller that moves Data between the processors RAM and some target. Formerly often some mass storage device, sometimes also graphic devices. 
 
Xilinx has a multi channel memory controller IP which is a key element for some DMA capable architecture.
The main question is if there's a gap between the memorys I/O bandwith and the CPUs maximum access speed.
If so, this gap can be used for DMA access without slowing down the CPU.
 
The performance of a multi channel DMA might be increased if you add small caches made from BRAMs for each channel.
The actual implementation, however, depends on your designs requirements and the capabilities of the devices (FPGA and RAM) you are going to use. Put up all the numbers from your requirements and look for the right devices.
Also remember that a FPGA can drive multiple memory banks independently.
 
__________________
What about that bidirectional thing?
Normally DMA is unidirectional, because you want to move data either in OR out of memory when looking at a single channel.
If you have separate channels for reading and writing, this is no problem unless the memory bandwith is sufficcient.
Again, think about multiple memory banks. And remember that DRAMs of any flavor (SD, DDR(2/3), QDR) perform best on block access (known as Burst Mode). So you will read a chunk of Data then write another chunk. You might be able to do both on the same adress at a time, but I doubt that this is what you want.
 
Have a nice synthesis
  Eilert
 
 
 

此外，
或者是否有可用的DMA IP核？
AXI DMA：http：//www.xilinx.com/products/intellectual-property/axi_dma.htm
AXI Central DMA：http：//www.xilinx.com/products/intellectual-property/axi_central_dma.htm
AXI视频DMA：http：//www.xilinx.com/products/intellectual-property/EF-DI-VID-DMA.htm
www.xilinx.com



以下为原文

In addition,
 
 
Or is there any DMA IP core available?
 
AXI DMA: http://www.xilinx.com/products/intellectual-property/axi_dma.htm
AXI Central DMA: http://www.xilinx.com/products/intellectual-property/axi_central_dma.htm
AXI Video DMA: http://www.xilinx.com/products/intellectual-property/EF-DI-VID-DMA.htm
www.xilinx.com

你好。
谢谢你的链接。
我对EDK相关设计的知识有限。
尽管使用MicroBlaze很有吸引力，但我不得不在没有微处理器的情况下进行设计（唯一可用的是调度程序或控制DMA的东西，而微处理器需要太多的资源。）
无论如何，谢谢你的回复。



以下为原文

Hi.
Thanks for your links. And I have sort of limited knowledge about EDK related design. Though using  MicroBlaze is attractive, I am forced to design without a microprocessor (The only available thing is a scheduler or something to control the DMA, and a microprocessor takes too many resource.) 
Anyway, thanks for your reply.

嗨，eilert。
谢谢你的建议。
一旦我认为应该有8个RAM和8个DMA来保持高带宽和高性能。
这听起来很甜蜜，然而，virtex-6 130T的总资源无法承受，因为我已经尝试编写可编程DMA并对其进行综合。
多通道内存控制器IP是否在http://www.xilinx.com/support/documentation/ip_documentation/xps_mch_emc.pdf中描述？
我去年在EDK尝试了MicroBlaze设计，我想知道IP是否只能用于EDK工具？
因此，出于某些原因，我无法将其作为解决方案。
调度程序可能足以在我的设计中控制DMA，因此不考虑CPU。
我相信瓶颈在于RAM和外围设备之间的总线。
那么应该进行权衡。
我将检查是否存在任何具有有限资源的高级DMA。
无论如何，非常感谢您的建议。



以下为原文

Hi, eilert.
Thanks for your advice. Once I thought there should be 8 RAMs and 8 DMA to keep a high bandwidth and high performance. That sounds sweet, however, the total resource of virtex-6 130T can't afford it, as I've tried to write a programmable DMA and synthesize it.
 
Is the multi channel memory controller IP the thing described in http://www.xilinx.com/support/documentation/ip_documentation/xps_mch_emc.pdf ?
I tried MicroBlaze design in EDK for last year and I wonder if the IP can only use with EDK tool? Therefore, I can't take it as a solution for some reasons. A scheduler might be enough to control the DMA in my design, thus CPU is out of consideration.
 
The bottleneck lies in the bus between RAMs and the peripheral devices, I believe. A tradeoff should be taken then. I'll check if there is any advanced DMA with limited resource. Anyway, thanks a lot for your advice.

conanandai100写道：
你好。
谢谢你的链接。
我对EDK相关设计的知识有限。
尽管使用MicroBlaze很有吸引力，但我不得不在没有微处理器的情况下进行设计（唯一可用的是调度程序或控制DMA的东西，而微处理器需要太多的资源。）
无论如何，谢谢你的回复。
不要贬低目前的讨论，我想指出你可以在没有处理器的情况下使用EDK（因此你仍然可以使用那些pcores，但设计你自己的总线主控来控制它们）。
有关示例，请参见xapp739
www.xilinx.com



以下为原文

conanandai100 wrote:
Hi.
Thanks for your links. And I have sort of limited knowledge about EDK related design. Though using  MicroBlaze is attractive, I am forced to design without a microprocessor (The only available thing is a scheduler or something to control the DMA, and a microprocessor takes too many resource.) 
Anyway, thanks for your reply.

Not to detract from the present disucssion, put I wanted to point out as a sidenote that you can use EDK without a processor (so you can still use those pcores, but design your own bus master to control them). See xapp739 for an example
 
www.xilinx.com