VHDL设计要注意什么

>我确信这是由于我的设计合成不好而不是
>我做出的逻辑/时间错误
如果合成设计极其不稳定并且可能产生在逻辑上不等同于源的结果，那么几乎所有业内人士都不会使用它。
是的，合成器中偶尔会出现一个错误，它会产生一个功能不相同的结果，但只有在消除了所有其他可能的原因后才能考虑这个错误。
>例如，有时候，一个模块中的一个小而不重要的变化
>带来另一个的运作，
这种行为通常是由于时序问题而不是由于合成器引起的。
每次放置和布线设计时，定时都将改变，如果交叉时钟域交叉没有得到正确处理，则设计中存在锁存器，或者时序约束是不完整的错误，可以在系统中看到。
你有没有完成这些？
1）检查合成器产生的每条WARNING信息以及布局和布线？
2）模拟您的原始VHDL源代码？
3）模拟合成的VHDL源代码？
4）使用反向注释时序模拟放置和布线设计？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> which I am certain that are due to bad synthesis of my design, and not
> logical/timing mistakes made by me
 
If synthesizing a design was exteremely unstable and likely to produce results that were not logically equivalent to the source it would not be used by nearly everyone in the industry.  Yes, there may be an occasional bug in a synthesizer that will produce a result that is not functionally equivalent, but this should be considered only after all other possible causes have been eliminated.
 
>For example, a small and unimportant change in one module, sometimes
> brings the operation of another,
 
This is the behavior is usually due to a timing issue and not due to a synthesizer.  Each time that the design is placed and routed the timing will change and if cross clock domain crossings are not properly handled, latches are present in the design or the timing constraints are incomplete errors may be seen in the system.
 
Have you done each of these?
1) Reviewed every WARNING message produced by the synthesizer and place and route?
2) Simulated your original VHDL source code?
3) Simulated the synthesized VHDL source code?
4) Simulated the placed and routed design with back annotated timing?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

首先，谢谢你的回复。
我已经缓冲了从另一个域进入时钟域的任何信号，其中两个连续的寄存器由目标频率计时。
我确信我的设计中没有锁存器，因为我已将所有信号分配为默认值，并且没有指示合成器警告中是否存在锁存器。
因为涉及很多外围设备，所以不容易模拟设计，除非我首先对所有外围设备进行建模，这非常麻烦。
关于时间限制，我必须承认我没有分配任何！
但我还要补充一点，我设计中涉及的所有时钟都低于50MHz。
是否有必要为这些频率分配时序约束？
我觉得在任何状态下都不应该读取状态机的输出，因为这对合成器来说有点混乱。
我对吗？
我想如果在某些状态下将信号视为输出，则不应将其视为任何状态的输入，除非在状态机外缓冲。
换句话说，信号应始终被视为状态机的输入或输出，但从不作为两者。
它是否正确？



以下为原文

First of all, thank you for your reply. I have buffered any signal that enters a clock domain from another domain with two successive registers clocked by the destination frequency. I am certain that there are no latches present in my design, because I have assigned all signals their default values, and there is no indication of presence of latches in the synthesizer warnings.
Because there are alot of peripheral devices involved, simulation of the design is not easily possible, unless I model all peripherals first, which is very cumbersome.
About the timing constraints, I must confess that I have not assigned any! But I should also add that all clocks involved in my design are under 50MHz. Is it necessary to assign timing constraints for such frequencies?
I have a feeling that none of the outputs of a state machine should be read in any state, because this is somehow confusing to the synthesizer. Am I right? I guess if a signal is treated as an output in some states, then it should not be treated as an input in any state, unless buffered outside the state machine. In other words, a signal should always be treated as either an input or an output of the state machine, but never as both. Is this correct?

farhad.rafraf写道：
因为涉及很多外围设备，所以不容易模拟设计，除非我首先对所有外围设备进行建模，这非常麻烦。
它可能很麻烦，并且可能会超出“免费”模拟工具支持的代码大小，但是对所有外围设备进行建模非常值得您花费时间。
您应该建立一个您使用的外围设备的仿真模型库。
写一次，多次使用。
关于时间限制，我必须承认我没有分配任何！
但我还要补充一点，我设计中涉及的所有时钟都低于50MHz。
是否有必要为这些频率分配时序约束？
绝对！
快速简便的解决方案是让FPGA在不考虑布线的情况下确保逻辑适合器件。
您可能很容易得到不符合50 MHz约束的逻辑。
总是限制时钟周期。
没有理由不这样做，而且周期约束最容易创建。
我觉得在任何状态下都不应该读取状态机的输出，因为这对合成器来说有点混乱。
我对吗？
我想如果在某些状态下将信号视为输出，则不应将其视为任何状态的输入，除非在状态机外缓冲。
换句话说，信号应始终被视为状态机的输入或输出，但从不作为两者。
它是否正确？
如果您的状态机的输出都不应该被读取，那么它不是很有用！
规则是：始终使用单个同步过程编写状态机。
刻录任何暗示的教科书或参考文献。
至于信号是特定状态机的输入和输出，我无法想象任何具有任何逻辑意义的情况。
假设你有一个信号foo。
foo在您机器的几种状态下分配。
在另一种状态下，机器旋转并等待foo为某个值。
如果foo不是该值，则永远不能将其设置为该值，因此机器被锁定。
当然，没有什么可以阻止你编写完全正确的代码。
这就是我们模拟的原因:)
----------------------------是的，我这样做是为了谋生。



以下为原文

farhad.rafraf wrote:
 
Because there are alot of peripheral devices involved, simulation of the design is not easily possible, unless I model all peripherals first, which is very cumbersome.
 
It may be cumbersome, and it will likely exceed the code size that the "Free" simulation tools support, but modeling ALL peripherals is well worth the time you spend doing so. You should build up a library of simulation models of the peripherals you use. Write once, use many times.
 
About the timing constraints, I must confess that I have not assigned any! But I should also add that all clocks involved in my design are under 50MHz. Is it necessary to assign timing constraints for such frequencies?
 
 
Absolutely! The quick and easy solution is for the FPGA to make sure the logic fits into the part without any consideration of routing. You could easily end up with logic that doesn't meet a 50 MHz constraint.
 
ALWAYS constrain for clock period. There is no reason not to, and besides, the period constraint is the easiest to create.
 
 
I have a feeling that none of the outputs of a state machine should be read in any state, because this is somehow confusing to the synthesizer. Am I right? I guess if a signal is treated as an output in some states, then it should not be treated as an input in any state, unless buffered outside the state machine. In other words, a signal should always be treated as either an input or an output of the state machine, but never as both. Is this correct?

If none of the outputs of your state machine should be read, then it's not very useful!
 
The Rule is: always write state machines with a single synchronous process. Burn any textbooks or references that suggest otherwise.
 
As for a signal being an input to and an output from a particular state machine, I can't envision any circumstance where that would make any logical sense. Say that you have a signal foo. foo is assigned in a couple of states in your machine. In another state, the machine spins and waits for foo to be a certain value. If foo is not that value, it can never be set to that value, so the machine is locked.
 
there's nothing stopping you from writing code that does exactly that, of course. This is why we simulate :)
----------------------------Yes, I do this for a living.

>我已经缓冲了从另一个域连续两次进入时钟域的任何信号
>由目标频率计时的寄存器。
这是一种能够将异步信号同步到同步域的亚稳态技术。
如果您已经为总线（或多个位）执行了此操作，并且期望所有数据位将在新的同步域中对齐，则此技术存在缺陷并将导致错误。
>我确信我的设计中没有锁存器，因为我已经分配了所有锁存器
>发出默认值信号，并且没有指示合成器警告中是否存在锁存器。
默认值不会影响设计中锁存器的错误推断。
您需要检查利用率报告，以查看设计中是否有意外的锁存器。
>因为涉及很多外围设备，所以不容易模拟设计
>可能，除非我先对所有外围设备进行建模，这非常麻烦。
好的，这意味着你没有模拟设计并确认它确实有效。
在将任何责任归咎于合成器以产生错误的逻辑之前，我会专注于此。
>关于时间限制，我必须承认我没有分配任何！
这是一个主要问题，您的设计无法保证正常运行。
>但我还要补充一点，我设计中涉及的所有时钟都低于50MHz。
是否有必要
>为这些频率分配时序约束？
是的，这是确保设计满足时间要求的必要条件。
>我感觉状态机的任何输出都不应该在任何状态下读取，因为
>这对合成器来说有点混乱。
我对吗？
连接到状态机输入的状态机输出是每个状态机中的基本概念，并且没有问题。
>我想如果在某些状态下将信号视为输出，则不应将其视为
>在任何状态下输入，除非在状态机外缓冲。
换句话说，信号应该
>始终被视为状态机的输入或输出，但从不作为两者。
它是否正确？
你似乎对一些基本的数字设计实践感到困惑。
我建议你在工作中咨询你的教授或同事，或者从一些基本的设计教程开始，以便在尝试使用大量外围设备进行复杂设计之前熟悉数字和FPGA设计的基本概念。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> I have buffered any signal that enters a clock domain from another domain with two successive
> registers clocked by the destination frequency.
 
This is a metastability technique to be able to synchronize an asynchronous signal into a synchronous domain.  If you have done this for a bus (or multiple bits) and expect that all of the data bits will be aligned in the new synchronous domain this technique is flawed and will result in errors.
 
> I am certain that there are no latches present in my design, because I have assigned all
> signals their default values, and there is no indication of presence of latches in the synthesizer warnings.
 
Default values no impact on incorrect inference of latches in a design.  You need to check the utilization reports to see if you have unintended latches in the design.  
 
> Because there are alot of peripheral devices involved, simulation of the design is not easily
> possible, unless I model all peripherals first, which is very cumbersome.
 
Ok, so this means that you have not simulated the design and confirmed that it actually works.  I would focus on this before assigning any blame to a synthesizer for incorrect logic generation.
 
> About the timing constraints, I must confess that I have not assigned any!
 
This is a major issue and your design will not have guarantee of functioning correctly.
 
> But I should also add that all clocks involved in my design are under 50MHz. Is it necessary to
> assign timing constraints for such frequencies?
 
Yes this is necessary to ensure that the design meets timing.
 
> I have a feeling that none of the outputs of a state machine should be read in any state, because
> this is somehow confusing to the synthesizer. Am I right?
 
State machines outputs connected to state machine inputs is a fundamental concept in every state machine and will have no issues.
 
> I guess if a signal is treated as an output in some states, then it should not be treated as an
> input in any state, unless buffered outside the state machine. In other words, a signal should
> always be treated as either an input or an output of the state machine, but never as both. Is this correct?

You seemed to be confused about some fundamental digital design practices.  I would suggest that you consult with your professor or a colleague at work or alternatively start with some basic design tutorials to familiarize yourself with the basic concepts of digital and FPGA design before attempting complicated designs withs lots of peripherals.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

>我已经缓冲了从另一个域连续两次进入时钟域的任何信号
>由目标频率计时的寄存器。
这是一种能够将异步信号同步到同步域的亚稳态技术。
如果您已经为总线（或多个位）执行了此操作，并且期望所有数据位将在新的同步域中对齐，则此技术存在缺陷并将导致错误。
>我确信我的设计中没有锁存器，因为我已经分配了所有锁存器
>发出默认值信号，并且没有指示合成器警告中是否存在锁存器。
默认值不会影响设计中锁存器的错误推断。
您需要检查利用率报告，以查看设计中是否有意外的锁存器。
>因为涉及很多外围设备，所以不容易模拟设计
>可能，除非我先对所有外围设备进行建模，这非常麻烦。
好的，这意味着你没有模拟设计并确认它确实有效。
在将任何责任归咎于合成器以产生错误的逻辑之前，我会专注于此。
>关于时间限制，我必须承认我没有分配任何！
这是一个主要问题，您的设计无法保证正常运行。
>但我还要补充一点，我设计中涉及的所有时钟都低于50MHz。
是否有必要
>为这些频率分配时序约束？
是的，这是确保设计满足时间要求的必要条件。
>我感觉状态机的任何输出都不应该在任何状态下读取，因为
>这对合成器来说有点混乱。
我对吗？
连接到状态机输入的状态机输出是每个状态机中的基本概念，并且没有问题。
>我想如果在某些状态下将信号视为输出，则不应将其视为
>在任何状态下输入，除非在状态机外缓冲。
换句话说，信号应该
>始终被视为状态机的输入或输出，但从不作为两者。
它是否正确？
你似乎对一些基本的数字设计实践感到困惑。
我建议你在工作中咨询你的教授或同事，或者从一些基本的设计教程开始，以便在尝试使用大量外围设备进行复杂设计之前熟悉数字和FPGA设计的基本概念。



以下为原文

> I have buffered any signal that enters a clock domain from another domain with two successive
> registers clocked by the destination frequency.
 
This is a metastability technique to be able to synchronize an asynchronous signal into a synchronous domain.  If you have done this for a bus (or multiple bits) and expect that all of the data bits will be aligned in the new synchronous domain this technique is flawed and will result in errors.
 
> I am certain that there are no latches present in my design, because I have assigned all
> signals their default values, and there is no indication of presence of latches in the synthesizer warnings.
 
Default values no impact on incorrect inference of latches in a design.  You need to check the utilization reports to see if you have unintended latches in the design.  
 
> Because there are alot of peripheral devices involved, simulation of the design is not easily
> possible, unless I model all peripherals first, which is very cumbersome.
 
Ok, so this means that you have not simulated the design and confirmed that it actually works.  I would focus on this before assigning any blame to a synthesizer for incorrect logic generation.
 
> About the timing constraints, I must confess that I have not assigned any!
 
This is a major issue and your design will not have guarantee of functioning correctly.
 
> But I should also add that all clocks involved in my design are under 50MHz. Is it necessary to
> assign timing constraints for such frequencies?
 
Yes this is necessary to ensure that the design meets timing.
 
> I have a feeling that none of the outputs of a state machine should be read in any state, because
> this is somehow confusing to the synthesizer. Am I right?
 
State machines outputs connected to state machine inputs is a fundamental concept in every state machine and will have no issues.
 
> I guess if a signal is treated as an output in some states, then it should not be treated as an
> input in any state, unless buffered outside the state machine. In other words, a signal should
> always be treated as either an input or an output of the state machine, but never as both. Is this correct?

You seemed to be confused about some fundamental digital design practices.  I would suggest that you consult with your professor or a colleague at work or alternatively start with some basic design tutorials to familiarize yourself with the basic concepts of digital and FPGA design before attempting complicated designs withs lots of peripherals.

正如mcgett指出的那样，RTL综合是一个非常可靠和可预测的过程。
虽然软件错误可能发生在任何程序中，但在我作为ASIC / FPGA设计人员的20年中，当合成工具生成不正确的逻辑时，我可能会遇到不到5次。
话虽这么说，使用RTL设计系统需要专业知识。
这是一个需要学习和正确学习的过程。
绝对必要的一件事是限制 - 我怀疑你所看到的任何不稳定性仅仅是由于缺乏约束。
任何频率都需要约束 - 无论多慢（50MHz甚至不那么慢）。
此外，你说的其他一些事情令人担忧。 
- 模块中没有多于一个状态机的要求（甚至不建议） 
- 在非常有限的情况下（即缓慢变化的单个数据位 - 从不是总线），从一个域到另一个域的信号的简单双重翻转就足够了 
- 尝试在没有事先模拟的情况下在实验室中进行调试很少会取得成功 - 是的，为所有外围设备编写模型非常耗时 
- 验证与编写RTL一样，都是一项工程工作 
- 我不遵循“读取状态机的输出” - 状态机输出只是存在，它们不是“读” 
- 根据需要将状态机输出用于任何目的是没有问题的 - 事实上，如果没有这个，状态机就没用了 
- 缓冲不会在RTL中“执行”任何操作 
- 我不知道信号如何既是输出又是状态机的输入......
基于这些，您可能需要找到一种方法来更多地了解RTL设计的基础知识。
理想情况下，这可以在导师的指导下进行，但（在这个时代）导师并不总是可用。
如果没有导师，那么关于RTL设计概念的好书可能会有所帮助（过去曾在这些论坛上提出过很多建议）。
祝你好运，
Avrum



以下为原文

As mcgett pointed out, RTL synthesis is a very reliable and predictable process. While software errors can happen in any program, in my 20 years as an ASIC/FPGA designer, I have probably encountered less than 5 occasions when a synthesis tool has generated incorrect logic.
 
That being said, designing a system using RTL needs expertise. It is a process that needs to be learned, and learned properly.
 
One thing that is ABSOLUTELY ESSENTIAL is constraints - my suspicion is that any instabilities you have seen are solely due to the lack of constraints. Constraints are required at ANY frequency - no matter how slow (and 50MHz isn't even that slow).
 
Also, some of the other things you have said are worrisome.
  - There is not requirement (nor is it even recommended) to have no more than one state machine in a module
  - Simple double flopping of signals from one domain to another is only sufficient under VERY limited circumstances (i.e. a slow changing single bit of data - never a bus)
  - Attempting to debug in the lab without prior simulation rarely leads to success - and yes, writing models for all your peripherals is time consuming
    - verification is as much of an engineering effort as writing RTL
  - I don't follow the "reading outputs of a state machine" - state machines outputs simply exist, they aren't "read"
    - there is no problem using the state machine output for any purpose as needed - in fact, without this, state machines are useless
  - Buffering doesn't "do" anything in RTL
  - I don't know how a signal can be both an output and an input of a state machine...
 
Based on these, you probably need to find a way to get some more exposure to the basics of RTL design. Ideally, this would be done under a mentor, but (in this day and age) mentors are not always available. If a mentor is not available, a good book on the concepts of RTL design would probably help (many have been suggested on these forums in the past).
 
Good luck,
 
Avrum

谢谢你们的评论。
所以我想在第一步我必须对我的设计应用时序约束，考虑到有多个时钟域，这是一项复杂的任务。
我会努力的。



以下为原文

Thank you guys for your comments. So I guess in the first step I'll have to apply timing constraints to my design, which is a complicated task, considering that there are multiple clock domains. I'll be working on that.

>有多个时钟域。“好吧，那里有你的问题......”你如何在这些时钟域之间传输数据？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

> there are multiple clock domains.

"Well, there's your problem right there..."

How are you transferring data between those clock domains?

------------------------------------------
"If it don't work in simulation, it won't work on the board."

我不知道我在时钟域之间传输信号时犯了错误。
因此，我现在已经改变了DCM输出频率，因此设计中没有不同步的EDGES（我使用18meg和72meg时钟）。
我想不应再有missync域的问题了。
我对吗？
我也确定了时间限制。
但问题仍然存在，即设计中的微小变化会导致不可预测的合成器行为。



以下为原文

I undrestand that I had made mistakes in transferring signals between the clock domains. Therefore I have now changed the DCM output frequencies so that there are no unsyncronous EDGES in the design (I am using 18meg and 72meg clocks). I suppose there should not be a problem of missync domains anymore. Am I right? I have also determined the timing constraints. But the problem still persists that a small change in the design leads to unpredictable synthesizer behaviour.