在哪个文件中应该定义端口l_data？

嗨，
我是这个领域的新手，使用spartan 3e入门套件和Xilinx ISE Design Suite 13.2来输出由pmod mic录制的音频文件。
我抓住了一个定制的IP，通过FSL挂钩i2s pmod和microblaze。
当我生成比特流时，我得到了
---
with local fileERROR：Xst：1933  - “C： Users  Jay  Documents  Xilinx  final_project_3  pcores  fsl_i2s_v1_00_a / hdl / verilog / i2s_out.v”模块：实例和模块定义之间的端口不匹配.ERROR：EDK：546
- 中止XST流程执行！
运行NGCBUILD ... IPNAME：clock_generator_0_wrapper INSTANCE：clock_generator_0 -C： Users  Jay  Documents  Xilinx  final_project_3  system.mhs第198行 -  RunningNGCBUILDPMSPEC  - 使用本地fileCommand行覆盖Xilinx文件：C： Xilinx  13.2  ISE_DS
ISE  bin  nt64  unwrapped  ngcbuild.exe -pxc3s500efg320-4 -intstyle silent -i -sd .. clock_generator_0_wrapper.ngc ../ clock_generator_0_wrapperReading NGO file“C：/ Users / Jay / Documents / Xilinx / final_project_3 / implementation /
clock_generator_0_wrapper / clock_generator_0_wrapper.ngc“...分区实施状态-------------------------------在此设计中未找到分区
.------------------------------- NGCBUILD设计结果摘要：错误数：0警告数：0Writing NGC file“
../clock_generator_0_wrapper.ngc“......完成NGCBUILD完成的总时间：1秒完成NGCBUILD完成的CPU时间：1秒写入NGCBUILD日志文件”../clock_generator_0_wrapper.blc"..NGCBUILD done.INFO:EDK:3509-
NCF文件不应该是修改的
d因为它们将被再生。
如果需要覆盖任何约束，则应通过修改data / system.ucf文件来完成。建立缓存...错误：EDK：440  -  platgen失败并出现错误！make：*** [implementation / system.bmm]
错误2Done！
---
我一直在努力确保外围设备的.mpd，.v和.vhd文件是正确的。
但是，我仍然收到此错误消息。
有人可以告诉我在哪个文件中应该定义端口l_data？
任何帮助表示赞赏。
谢谢。
fsl_i2s_v1_00_a / |  - 数据|
|  -  fsl_i2s_v2_1_0.mpd |
` -  fsl_i2s_v2_1_0.pao`-- hdl |  -  verilog |
|  -  clkgen.v |
` -  i2s_out.v`  -  vhdl`  -  fsl_i2s.vhd
fsl_i2s_v1_00_a.zip 5 KB



以下为原文

Hi,
I 'm new to this area and using spartan 3e starter kit and Xilinx ISE Design Suite 13.2 to output audio file which is recorded by pmod mic. I have grabbed a customed IP which hooks i2s pmod and microblaze through FSL. When I generated bitstream, I got


---

with local file

ERROR:Xst:1933 - "C:UsersJayDocumentsXilinxfinal_project_3pcoresfsl_i2s_v1_00_a/hdl/verilog/i2s_out.v" Module : mismatch on port between instance and module definition.
ERROR:EDK:546 - Aborting XST flow execution!

Running NGCBUILD ...
IPNAME:clock_generator_0_wrapper INSTANCE:clock_generator_0 -
C:UsersJayDocumentsXilinxfinal_project_3system.mhs line 198 - Running
NGCBUILD
PMSPEC -- Overriding Xilinx file
with local file


Command Line: C:Xilinx13.2ISE_DSISEbinnt64unwrappedngcbuild.exe -p
xc3s500efg320-4 -intstyle silent -i -sd .. clock_generator_0_wrapper.ngc
../clock_generator_0_wrapper

Reading NGO file
"C:/Users/Jay/Documents/Xilinx/final_project_3/implementation/clock_generator_0_
wrapper/clock_generator_0_wrapper.ngc" ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGCBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGC file "../clock_generator_0_wrapper.ngc" ...
Total REAL time to NGCBUILD completion:  1 sec
Total CPU time to NGCBUILD completion:   1 sec

Writing NGCBUILD log file "../clock_generator_0_wrapper.blc"...

NGCBUILD done.
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
   If any constraint needs to be overridden, this should be done by modifying
   the data/system.ucf file.

Rebuilding cache ...
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system.bmm] Error 2
Done!
---


I have been trying to make sure that that my .mpd , .v and .vhd files for peripheral is correct. However, I still got this error message. Could anyone kindly tell me in which file the port l_data should be defined? Any help is appreciated. Thanks.


fsl_i2s_v1_00_a/
|-- data
|   |-- fsl_i2s_v2_1_0.mpd
|   `-- fsl_i2s_v2_1_0.pao
`-- hdl
    |-- verilog
    |   |-- clkgen.v
    |   `-- i2s_out.v
    `-- vhdl
        `-- fsl_i2s.vhd
            fsl_i2s_v1_00_a.zip ‏5 KB