接口virtex 5 FXT与外部快速比较器连接问题

钱德拉，
200ps非常小。
我希望你需要某种外部脉冲展宽器或内聚电路。
将这么短的信号带入FPGA是非常棘手的，然后我不确定你能用它做什么（它肯定超过了IOB或CLB中DFF的最大频率，脉冲宽度需求）。
我想你可以构建一个手放置和路由单元来锁定事件，但这将非常棘手，并且完全超出任何规范或性能保证。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Chandra,
 
200ps is pretty tiny.  I would expect you to need some sort of external pulse stretcher or lacthing circuit.  It will be very tricky to bring such a short signal into the FPGA, and then I am unsure what you can do with it (it sertainly exceeds the maximum frequency, pulse width needs of the DFF in the IOB or CLB).  I suppose you might be able to construct a hand placed and routed cell to latch the event, but that will be very tricky, and be quite outside any specifications, or guarantees of performance.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

嗨奥斯汀，
我观察到ADCMP573支持RSPECL标准。
ADCMP573的RSPECL标准信号是否可以映射到Virtex5 FXT中的LVPECL。它们是否兼容？
问候
钱德拉



以下为原文

Hi Austin,
I observe ADCMP573 supporting RSPECL standard. Can a signal with RSPECL standard from ADCMP573  be  mapped to LVPECL in Virtex5 FXT.Are they compatible?
regards
chandra
 

ADCMP573的RSPECL标准信号是否可以映射到Virtex5 FXT中的LVPECL。它们是否兼容？
LVPECL输入电平在Virtex-5数据表DS202中规定。
- 鲍勃埃尔金德
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以下为原文

Can a signal with RSPECL standard from ADCMP573  be  mapped to LVPECL in Virtex5 FXT.Are they compatible?
 
LVPECL input levels are specified in the Virtex-5 datasheet, DS202.
 
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