在同步设计中使用占空比不均匀的时钟是否可行

嗨维沙尔，
当一个人写关于使用两个时钟边沿时，主要有两种可能性。
1）在有益的情况下明智地使用这种方法对FPGA技术有深刻理解的人。
2）由于缺乏对同步设计原理的理解，有些人有一些狡猾的想法和倾向于弄乱设计。
DCM和其他时钟源通常仅产生50％的占空比信号。
一个原因是它们还能够在90度，180度和270度产生锁相移位信号，用于特殊目的。
如果您碰巧以某种方式生成10％占空比时钟，则需要在某个全局时钟网上获取它。
否则，歪斜效应会破坏您的设计功能。
在两个时钟边沿上只有10％的占空比和进程触发会导致仅允许非常小的延迟的som路径（除非时钟频率稍低）。
这可能会导致时序收敛的麻烦。
我已经假设您有多个触发这样的进程： 
永远@（posedge clk） 
... 
永远@（negedge clk） 
...
因为 
永远@（clk）
不会合成。
FPGA只是没有DDR-FF（I / O目的除外）
你需要这种奇怪的时钟方案的特殊设计是什么？
有一个很好的综合 
Eilert



以下为原文

Hi Vishal,
mainly there are two possibilities when one writes about using both clock edges.
1) Someone with a high understanding of FPGA technologie using this method wisely when benefitial.
2) Someone with some cunning ideas and a tendency to mess up a design due to a lack of understanding the principles of synchronous design.
 
DCMs and other clock sources in general only create 50% duty cycle signals. One reason is that they are also able to generate phase locked shifted signals on 90, 180, and 270 degrees, for special purposes.
If you happen to generate a 10% duty cycle clock somehow, you need to get it on some global clock net. Otherwise skew effects would mess up your design function.
 
Having only 10 % duty cycle and processes triggering on both clock edges results in som paths that allow only for a very small delay (unless the clock frequency is somewhat low). This can cause trouble for timing closure.
 
I'm already assuming that you have multiple processes triggerd like this:
  always @(posedge clk)
      ...
  always @(negedge clk)
     ...
because
  always @(clk)
wouldn't work in synthesis. FPGAs just don't have DDR-FFs (except for I/O purposes)
 
What's your special design that would require such a strange clocking scheme?
 
Have a nice synthesis
  Eilert

嗨艾勒特， 
感谢您的建议，我正在使用这些不均匀的时钟源，因为前一阶段的数据可以根据该时钟使用，而是我可以使用此脉冲（不均匀时钟）作为条件来执行我的主时钟操作作为始终块中的参考
。



以下为原文

hi  Eilert,
                 Thanks for the suggestion, I am using these uneven clock sources because the data from the previous stage is available according to that clock, instead can i use this pulse(uneven clock) as condition to perform my operations with master clock as reference in always block.
 

这个时钟有多快？
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

How fast is this clock?

------------------------------------------
"If it don't work in simulation, it won't work on the board."

我正在使用这些不均匀的时钟源，因为前一级的数据可以根据该时钟使用，而是可以使用此脉冲（不均匀时钟）作为条件来执行我的操作，主时钟作为始终块中的参考。
请更具体一点。
时钟有许多时序属性，请注意适用的属性。
输入数据是否来自公共时基？
输入数据是否对齐？
或输入数据的相位对齐是否发生变化（变量偏斜）？
时钟/数据去偏移功能在FPGA系列之间有所不同。
您是否考虑过特定​​的设备目标？
这是一个理论或学术设计作为学校项目或论文的一部分，还是一个必须实现和运作的商业设计？
底线：请描述各种输入数据的明显时序错位的性质和原因。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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你读过手册了吗？
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以下为原文

I am using these uneven clock sources because the data from the previous stage is available according to that clock, instead can i use this pulse(uneven clock) as condition to perform my operations with master clock as reference in always block.
 
Please be more specific.  There are a number of timing attributes of clocks, please note which attributes apply.
 
Are input data sourced from a common timebase or not?
Are input data phase aligned or not?  Or does phase alignment of input data change (variable skew)?
 
There are clock/data de-skewing capabilities which vary between the FPGA families.  Do you have a specific device target in mind?
 
Is this a theoretical or academic design as part of a school project or thesis, or is this a commercial design which must be realised and operational?
 
Bottom line:  please describe the nature and cause of the apparent timing misalignment of the various input data.
 
-- Bob Elkind
SIGNATURE:
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8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢鲍勃， 
它是一个有效信号，表示数据仅在信号为高电平时才有效，为了在下一阶段处理它，我使用它有下一个模块的时钟源。
总的来说，我想知道在始终阻塞中使用占空比不均匀的时钟是否正确并对其执行边沿操作。



以下为原文

thanks bob,
                       its a valid signal indicating data is valid only when signal is high , for processing it in next stages i am using it has clock source for the next module. On general note i want to know whether it is right to use a clock with uneven duty cycle in always block and perform edge operations on it.

我不明白你的回答。
你了解我的（以前发布的）问题吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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你读过手册了吗？
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如果我写一篇好文章，那么我一无所获。



以下为原文

I did not understand your response.  Did you understand my (previously posted) questions?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨，
从你现在写的一些东西我怀疑你将在你的设计中做一些令人讨厌的事情。
（使用一些稍微延迟的DataValid信号为一些连续的电路阶段提供时钟......让我的脊椎颤抖）
也许如果您提供一些代码示例，我们可以更好地理解并明确地给出您对设计的评论。
有一个很好的综合 
Eilert



以下为原文

Hi,
from the few things you have written now I'm suspecting that you are going to do something nasty in your design.
(using some slightly delayed DataValid signal to clock some consecutive circuit stage...gives me a shiver down my spine)
 
Maybe if you provide a little code example we can understand better and explicitly give you comments on your design.
 
Have a nice synthesis
  Eilert

使用一些稍微延迟的DataValid信号为一些连续的电路阶段提供时钟......让我的脊椎发抖
eilert能正确理解你的意图吗？
如果是这样，为什么在这个帖子的第一篇文章中没有说明这一点？
如果确实如此，则应该废弃并重新开始讨论。
以下是讨论的基本起点：
1.您的输入信号是什么？
2.您的系统时钟是什么（以及它与输入信号的关系）
你想要实现什么？
4.这是一个教学课程练习，还是你有一个特定的产品设计？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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不要在多个论坛上发布相同的问题。
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学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
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您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

using some slightly delayed DataValid signal to clock some consecutive circuit stage...gives me a shiver down my spine
 
Does eilert understand your intentions correctly?  If so, why wasn't this stated in the very first post in this thread?
 
If this is indeed the case, this discussion should be scrapped and re-started.
Here is a basic starting point for discussion:
 
1.  What are your input signals
2.  What is your system clock (and how does it relate to the input signals)
3.  What are you trying to achieve
4.  Is this a teaching course exercise, or do you have a specific product design in mind?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

这是代码片段，
总是@（negedge valid_out_new或negedge ASYNC_RESET）开始if（！ASYNC_RESET）开始energy2_1 best_tm结束否则if（best_tm_valid_fin）开始energy2_1 best_tm结束否则if（（（Avgiqsq [timing_index_valid]）> energy2））开始energy2_1 best_tm end end here valid_out_new has
循环10％，循环90％



以下为原文

here is the code snippet,
 
  always @(negedge valid_out_new or negedge ASYNC_RESET)
           begin
            if(!ASYNC_RESET)
                begin
                 energy2_1  <=  28'd0;  
                 best_tm <= 3'd0;      
               end
            else
            if(best_tm_valid_fin)
                begin
                 energy2_1  <=  28'd0;
                  best_tm <= best_tm;
                end
            else
            if(((Avgiqsq[timing_index_valid])> energy2))
                 begin
                   energy2_1<=(Avgiqsq[timing_index_valid]);
                   best_tm<=i_new;
                end
          end
here valid_out_new has 10% on cycle and 90% off cycle

请提供一些有关您的代码段要实现的功能的说明。
也：
1.什么是数据输入比特率。
2.什么是内部（FPGA）逻辑系统时钟频率
3. VALID输入信号的脉冲宽度是多少
我会问这一次，然后就此问题让你独自一人：你真的非常聪明能干，你的代码中不需要评论吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Please provide some explanation of what function your code snippet is intended to implement.
 
Also:
1.  What is data input bit-rate.
2.  What is internal (FPGA) logic system clock frequency
3.  What is pulse width of the VALID input signal
 
I will ask this once, and then leave you alone on the matter:  Are you really so brilliant and capable that you have no need for comments in your code?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨，
Bob是对的，这段代码片段没有其他信息也没用。
无论valid_out_new信号的占空比是多少，这总是阻止它自己是好的。
但...
值得怀疑的是，这个信号是你唯一的时钟信号（并通过时钟网络路由），或者，如果你有其他时钟网络的其他时钟，这些时钟之间的关系如何。
（你如何处理时钟域之间的数据传输）。
当然，你的时钟频率会很有趣。
此外，您是否了解同步设计中流水线的概念？
有一个很好的综合 
Eilert



以下为原文

Hi,
Bob is right, this code snippet is useless without additional information.
This always block for itself is ok, no matter what the duty cycle of the valid_out_new signal is.
But...
The questionable point is wether this signal is your only clock signal (and routed over a clock net) or, if you have other clocks for other always blocks, how is the relation between these clocks. (And how are you dealing with data transfer between clock domains).
And of course the frequency of your clocks would be interesting.
 
Besides, do you know about the concept of pipelining in a synchronous design?
 
Have a nice synthesis
  Eilert

“这里是代码片段”我很高兴它在Verilog中，所以我不明白它的全部恐怖！
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

"here is the code snippet"

I'm glad it is in Verilog so that I do not understand the full horror of it!
------------------------------------------
"If it don't work in simulation, it won't work on the board."

vishalk写道：
这是代码片段，
总是@（negedge valid_out_new或negedge ASYNC_RESET）开始if（！ASYNC_RESET）开始energy2_1 best_tm结束否则if（best_tm_valid_fin）开始energy2_1 best_tm结束否则if（（（Avgiqsq [timing_index_valid]）> energy2））开始energy2_1 best_tm end end here valid_out_new has
循环10％，循环90％
哇，那段代码很糟糕。
我是认真的。
它对valid_out_new的下降沿很敏感，但该过程对该信号没有任何作用。
----------------------------是的，我这样做是为了谋生。



以下为原文

vishalk wrote:
here is the code snippet,
 
  always @(negedge valid_out_new or negedge ASYNC_RESET)
           begin
            if(!ASYNC_RESET)
                begin
                 energy2_1  <=  28'd0;  
                 best_tm <= 3'd0;      
               end
            else
            if(best_tm_valid_fin)
                begin
                 energy2_1  <=  28'd0;
                  best_tm <= best_tm;
                end
            else
            if(((Avgiqsq[timing_index_valid])> energy2))
                 begin
                   energy2_1<=(Avgiqsq[timing_index_valid]);
                   best_tm<=i_new;
                end
          end
here valid_out_new has 10% on cycle and 90% off cycle

Wow, that code is crap. I am serious. It's sensitive to the falling edge of valid_out_new, yet the process does nothing with that signal.
----------------------------Yes, I do this for a living.

vishalk写道：
喜 
在同步设计中使用占空比不均匀的时钟是否可行，我使用这些时钟在上升沿和下降沿执行操作。
我使用这些脉冲作为总是块的时钟。
请建议。
谢谢，
维沙尔
要回答这个具体问题：是的，你可以。
但是，如果需要使用两个边缘，则不希望使用这样的时钟。
为什么？
因为占空比也直接设置时钟的相对边缘之间的最大允许逻辑延迟。
考虑具有10％占空比的100 MHz时钟。
这意味着在两个上升沿或两个下降沿之间有10 ns的时钟周期。
但10 ns的10％是1 ns（这是准时）。
现在，想想：上升边缘和下一个下降边缘之间的时间是多少？
是的，你是对的，它是1 ns。
这意味着逻辑在时钟上升沿之后从tCO传播到下降沿之前的设置的允许时间为1 ns。
这与1 GHz时钟的周期相同！
您认为您的FPGA速度如此之快吗？
----------------------------是的，我这样做是为了谋生。



以下为原文

vishalk wrote:
hi,
      Is it feasible to use clocks with uneven duty cycle in synchronous designs, i am using these clocks to perform operations on rising edge and falling edge. I am using these pulses as clocks in always blocks . Please suggest.
 
thanks,
vishal
 
 

To answer this specific question: yes, you can. However, you don't want to use such a clock if you need to use both edges. Why? Because the duty cycle also directly sets the maximum allowable logic delay between the opposite edges of the clock.
 
Consider a 100 MHz clock with a 10% duty cycle. This implies a 10 ns clock period between two rising or two falling edges. But 10% of 10 ns is 1 ns (which is the on time). Now, think: what is the time between a rising edge and the next falling edge? Yes, you are right, it is 1 ns. That means that the allowable time for logic to propagate from the tCO after the rising edge of the clock to the setup before the falling edge is 1 ns. This is the same period as for a 1 GHz clock! Do you think your FPGA is that fast?
----------------------------Yes, I do this for a living.

哇，那段代码很糟糕。
我是认真的。
它对valid_out_new的下降沿很敏感，但该过程对该信号没有任何作用。
太苛刻了。
Valid_out_new输入信号用作此过程的时钟。
这种编码没有技术故障，它紧跟在具有时钟和异步有源低电平复位的D-FF的ISE模板之后。
真正的问题更为笼统和概念性。
Vishalk是Xilinx未来的重要客户，在我们驱逐他们之前，让我们给vishalk一个机会。
我们之前帮助那些编码熟练程度低得多的人。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Wow, that code is crap. I am serious. It's sensitive to the falling edge of valid_out_new, yet the process does nothing with that signal.
 
Too harsh.  Valid_out_new input signal is used as a clock for this process.  There is no technical fault with this coding, it closely follows the ISE template for a D-FF with negedge clock and async active low reset.  The real issues are more general and conceptual.
 
Vishalk is a valued future Xilinx customer, let's give vishalk a chance before we drive him/her away.  We've helped folks with much less coding proficiency before.
 
-- Bob Elkind
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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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