在Virtex II pro中的存储器块SRAM之后添加多路复用器后无法看到数据

请参阅以下我的计划：
data1_i到data4_i是来自寄存器的数据，我可以在多路复用器之后读取这些数据。
data5_i是多路复用器之后的SRAM数据。
你在这段代码中看到了问题吗？
图书馆IEEE;
使用IEEE.STD_LOGIC_1164.ALL;
使用IEEE.STD_LOGIC_ARITH.ALL;
使用IEEE.STD_LOGIC_UNSIGNED.ALL;
实体MUX是
端口（data1_i：在STD_LOGIC_VECTOR中（31 downto 0）;
data2_i：在STD_LOGIC_VECTOR中（31 downto 0）;
data3_i：在STD_LOGIC_VECTOR中（31 downto 0）;
data4_i：在STD_LOGIC_VECTOR中（31 downto 0）;
data5_i：在STD_LOGIC_VECTOR中（31 downto 0）;
line_s：在STD_LOGIC_VECTOR（2 downto 0）;
data_o：out STD_LOGIC_VECTOR（31 downto 0）
）;
结束MUX;
体系结构MUX的行为是
开始
处理（line_s，data1_i，data2_i，data3_i，data4_i，data5_i）
开始
case line_s是

当“001”=> data_o data_o data_o data_o data_o data_o 以下为原文


See as below my program:
 

data1_i to data4_i are data from registers, I can read these datas after the multiplexor. data5_i is the data of the SRAM after the mux. Do you see a problem in this code ?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX is
Port ( data1_i : in STD_LOGIC_VECTOR (31 downto 0);
data2_i : in STD_LOGIC_VECTOR (31 downto 0);
data3_i : in STD_LOGIC_VECTOR (31 downto 0);
data4_i : in STD_LOGIC_VECTOR (31 downto 0);
data5_i : in STD_LOGIC_VECTOR (31 downto 0);
line_s : in STD_LOGIC_VECTOR (2 downto 0);
data_o : out STD_LOGIC_VECTOR (31 downto 0)
);
end MUX;
architecture Behavioral of MUX is
begin
　
　
　
process(line_s,data1_i,data2_i,data3_i,data4_i,data5_i)
begin
case line_s is
when "001" => data_o <= data1_i;
when "010" => data_o <= data2_i;
when "011" => data_o <= data3_i;
when "100" => data_o <= data4_i;
when "101" => data_o <= data5_i;
when others => data_o <= "11111111111111111111111111111111";
end case;
end process;
end Behavioral;