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我购买了cvk-pro2套件并开始使用ise13的显示端口源策略制定者;
当使用核心生成器在4通道中生成displayport tx时（尚未尝试其他组合，但这是典型的h / w配置），我在这些行中得到了错误消息： 错误：sim - 无法评估Tcl命令： :: xilinx :: sim :: generation :: generateCore {com.xilinx.ip.displayport_v1_2.displayport_v1_2} {displayport_v1_2a} {ALL} 错误：sim - 生成期间发现错误。 这是从头开始的完整日志： 欢迎来到Xilinx CORE Generator。 帮助系统初始化。 IP目录已重新加载。 CoreGen尚未配置任何用户存储库。 CoreGen已配置以下Xilinx存储库： - 'C： Xilinx 13.1 ISE_DS ISE coregen '[xil_index.xml] IP目录已重新加载。 打开项目文件C： Xilinx XAPP493 ise_top_level ipcore_dir coregen.cgp。 自定义和生成（在原始项目设置下） 信息：sim：927 - 从'C： Xilinx 13.1 ISE_DS ISE coregen ip xilinx network com xilinx ip生成'xilinx.com:ip:displayport:1.2'的组件实例'displayport_v1_2' displayport_v1_2 displayport_v1_2.xcd”。 定制IP ...... 版本13.1 - Xilinx CORE Generator IP GUI启动器O.40d（nt） 版权所有（c）1995-2011 Xilinx，Inc。保留所有权利。 找到组件的硬件评估许可证。 生成的 某些设备运行后，设计将停止在编程设备中运行 一段的时间。 这允许您在硬件中评估组件。 你是 鼓励许可此组件。 生成了此核心的许可证 for jackhsieh98@yahoo.com于03/15/2011由被许可方负责 该核心遵守适用许可的所有条款和条件 使用此核心时的协议。 有关订购信息，请参阅 该组件的产品页面：www.xilinx.com 初始化IP模型...... 完成初始化IP模型。 完成定制。 生成IP ... 警告：sim：975 - 您正在使用已被新版本替换的DisplayPort 1.2。 此版本的核心将在未来版本中删除。 不支持处于此状态的核心。 配置displayport_v1_2a dport_link的文件... 整理displayport_v1_2a的核心文件 整理displayport_v1_2a的核心文件 收集displayport_v1_2a dport_link的HDL文件... 为dport_link创建XST项目... 为dport_link创建XST脚本文件... 为dport_link创建XST实例化文件... 为dport_link运行XST ... 警告：coreutil-dST dport_link失败。 错误：Xst：439 - C： TEMP 中没有写访问权限 从内部调用 “runXST $ ComponentName GenerationOptions $ TopLevel” （程序“deliverXSTNetlist”第15行） 从内部调用 “deliverXSTNetlist $ componentName GenerationOptions”dport_link“” （程序“components :: displayport_v1_2a :: generate”第67行） 从内部调用 “组件:: $ {componentName}所需::生成” （程序“:: xilinx :: sim :: generation :: generateCore”第84行） 从内部调用 “:: xilinx :: sim :: generation :: generateCore {com.xilinx.ip.displayport_v1_2.displayport_v1_2} {displayport_v1_2a} {ALL}” 错误：sim - 无法评估Tcl命令： :: xilinx :: sim :: generation :: generateCore {com.xilinx.ip.displayport_v1_2.displayport_v1_2} {displayport_v1_2a} {ALL} 错误：sim - 生成期间发现错误。 以上来自于谷歌翻译 以下为原文 i purchased cvk-pro2 kit and started with display port source policy maker with ise13; when using core generator to generate the displayport tx in 4-lane (have not tried other combination yet but this is typical h/w configuration), i got the error msg in these lines: ERROR:sim - Unable to evaluate Tcl command: ::xilinx::sim::generation::generateCore {com.xilinx.ip.displayport_v1_2.displayport_v1_2} {displayport_v1_2a} {ALL} ERROR:sim - Error found during generation. here is the completed log from the beginning: Welcome to Xilinx CORE Generator. Help system initialized. The IP Catalog has been reloaded. CoreGen has not been configured with any user repositories. CoreGen has been configured with the following Xilinx repositories: - 'C:Xilinx13.1ISE_DSISEcoregen' [xil_index.xml] The IP Catalog has been reloaded. Opening project file C:XilinxXAPP493ise_top_levelipcore_dircoregen.cgp. Recustomize and Generate (Under Original Project Settings) INFO:sim:927 - Generating component instance 'displayport_v1_2' of 'xilinx.com:ip:displayport:1.2' from 'C:Xilinx13.1ISE_DSISEcoregenipxilinxnetworkcomxilinxipdisplayport_v1_2displayport_v1_2.xcd'. Customizing IP... Release 13.1 - Xilinx CORE Generator IP GUI Launcher O.40d (nt) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. Hardware Evaluation license for component design will cease to function in the programmed device after operating for some period of time. This allows you to evaluate the component in hardware. You are encouraged to license this component. The license for this core was generated for jackhsieh98@yahoo.com on 03/15/2011It is the responsibility of the Licensee of this core to adhere to all terms and conditions of the applicable license agreement when using this core. For ordering information, please refer to the product page for this component on: www.xilinx.com Initializing IP model... Finished initializing IP model. Finished Customizing. Generating IP... WARNING:sim:975 - You are using DisplayPort 1.2 which has been replaced with a new version. This version of the core will be removed in a future release. Cores in this state are not supported. Configuring files for displayport_v1_2a dport_link... Collating core files for displayport_v1_2a Collating core files for displayport_v1_2a Gathering HDL files for displayport_v1_2a dport_link... Creating XST project for dport_link... Creating XST script file for dport_link... Creating XST instantiation file for dport_link... Running XST for dport_link... WARNING:coreutil - XST failed for dport_link. ERROR:Xst:439 - No write access in C:TEMP invoked from within "runXST $ComponentName GenerationOptions $TopLevel" (procedure "deliverXSTNetlist" line 15) invoked from within "deliverXSTNetlist $componentName GenerationOptions "dport_link"" (procedure "components::displayport_v1_2a::generate" line 67) invoked from within "components::${ComponentName}::generate" (procedure "::xilinx::sim::generation::generateCore" line 84) invoked from within "::xilinx::sim::generation::generateCore {com.xilinx.ip.displayport_v1_2.displayport_v1_2} {displayport_v1_2a} {ALL}" ERROR:sim - Unable to evaluate Tcl command: ::xilinx::sim::generation::generateCore {com.xilinx.ip.displayport_v1_2.displayport_v1_2} {displayport_v1_2a} {ALL} ERROR:sim - Error found during generation. 
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Hi.My错误消息＃1是：＃1 [CoreGen尚未配置任何用户存储库.CoreGen已配置以下Xilinx存储库： - 'C： Xilinx 13.1 ISE_DS ISE coregen '[]
信息：sim：927 - 从'C： Xilinx 13.1 ISE_DS ISE coregen ip xilinx primary com xilinx ip生成'xilinx.com:ip:c_counter_binary:11.0'的组件实例'cnt_50m' c_counter_ binary_v11_0 component.xml'。执行Tcl生成器...完成执行Tcl生成器。执行Tcl生成器... INFO：sim - 解析'cnt_50m'的泛型... INFO：sim - 将外部泛型应用于'cnt_50m' ...完成执行Tcl生成器。执行Tcl生成器... INFO：sim - 为'cnt_50m'提供相关文件...完成执行Tcl生成器。执行Tcl生成器... INFO：sim - 生成'cnt_50m'的实现网表 ... INFO：sim - 为'cnt_50m'预处理HDL文件...错误：sim - C： TEMP ERROR中无写访问：sim - 执行Tcl generator.ERROR：SIM失败 - 无法生成'cnt_50m ”。 执行Tcl生成器失败。 ]请生成C： temp 和Rerty..Below是消息＃2：＃2 [CoreGen尚未配置任何用户存储库.CoreGen已配置以下Xilinx存储库： - 'C： Xilinx 13.1 ISE_DS ISE coregen '[] INFO：sim：927 - 从'C： Xilinx 13.1 ISE_DS ISE coregen ip 生成'xilinx.com:ip:c_counter_binary:11.0'的组件实例'cnt_50m' xilinx primary com xilinx ip c_counter_ binary_v11_0 component.xml'。执行Tcl生成器...完成执行Tcl生成器。执行Tcl生成器... INFO：sim - 解析'cnt_50m'的泛型... INFO： sim - 将外部泛型应用于'cnt_50m'...完成执行Tcl生成器。执行Tcl生成器... INFO：sim - 为'cnt_50m'提供相关文件...完成执行Tcl生成器。执行Tcl生成器... INFO： sim - 为'cnt_50m'生成实现网表... INFO：sim - 预处理'cnt_50m'的HDL文件...完成执行Tcl生成器。执行Tcl生成器...完成执行Tcl生成器.Execu ting Tcl生成器...完成执行Tcl生成器。执行Tcl生成器... INFO：sim - 为'cnt_50m'编写VHO实例化模板... INFO：sim - 为'cnt_50m'编写VEO实例化模板...完成执行Tcl generator.Executing Tcl generator ... INFO：sim - 为'cnt_50m'编写VHDL行为仿真模型...警告：sim - Verilog仿真文件类型'Behavioral'对此核心无效。 覆盖模拟文件类型'Structural'.INFO：sim - 为'cnt_50m'编写Verilog结构仿真模型...完成执行Tcl生成器。生成ASY原理图符号...初始化IP模型...完成初始化IP模型。完成生成 ASY原理图符号。执行Tcl生成器...信息：sim - 为'cnt_50m'生成SYM原理图符号...完成执行Tcl生成器。生成元数据文件...完成生成元数据文件。生成ISE项目...完成生成ISE project.Generating README file ...创建自述文件'./tmp/_cgcnt_50m_readme.txt'.Finished生成README文件。生成FLIST文件...完成FLIST文件生成。准备输出目录...完成准备输出目录。启动 README查看器...启动自述文件查看器。将文件移动到输出目录...完成移动文件到输出目录项目'C： mywork ipcore_dir cnt_50m.cgp'的文件文件。核心生成器创建命令已成功完成LUN：HDLCompiler： 169 3 - 将Verilog文件“C：/mywork/ipcore_dir/cnt_50m.v”分析到库workINFO：HDLCompiler：1061 - 将VHDL文件“C：/mywork/ipcore_dir/cnt_50m.vhd”解析为库workINFO：ProjectMgmt：659 - 解析设计层次成功完成。祝你好运！ 以上来自于谷歌翻译 以下为原文 Hi. My Error Message #1 is : #1 [ CoreGen has not been configured with any user repositories. CoreGen has been configured with the following Xilinx repositories: - 'C:Xilinx13.1ISE_DSISEcoregen' [] INFO:sim:927 - Generating component instance 'cnt_50m' of 'xilinx.com:ip:c_counter_binary:11.0' from 'C:Xilinx13.1ISE_DSISEcoregenipxilinxprimarycomxilinxipc_counter_ binary_v11_0component.xml'. Executing Tcl generator... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Resolving generics for 'cnt_50m'...INFO:sim - Applying external generics to 'cnt_50m'... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Delivering associated files for 'cnt_50m'... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Generating implementation netlist for 'cnt_50m'... INFO:sim - Pre-processing HDL files for 'cnt_50m'... ERROR:sim - No write access in C:TEMP ERROR:sim - Failed executing Tcl generator. ERROR:sim - Failed to generate 'cnt_50m'. Failed executing Tcl generator. ] Please make C:temp and Rerty.. Below is Message #2 : #2 [ CoreGen has not been configured with any user repositories. CoreGen has been configured with the following Xilinx repositories: - 'C:Xilinx13.1ISE_DSISEcoregen' [] INFO:sim:927 - Generating component instance 'cnt_50m' of 'xilinx.com:ip:c_counter_binary:11.0' from 'C:Xilinx13.1ISE_DSISEcoregenipxilinxprimarycomxilinxipc_counter_ binary_v11_0component.xml'. Executing Tcl generator... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Resolving generics for 'cnt_50m'... INFO:sim - Applying external generics to 'cnt_50m'... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Delivering associated files for 'cnt_50m'... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Generating implementation netlist for 'cnt_50m'... INFO:sim - Pre-processing HDL files for 'cnt_50m'... Finished executing Tcl generator. Executing Tcl generator... Finished executing Tcl generator. Executing Tcl generator... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Writing VHO instantiation template for 'cnt_50m'... INFO:sim - Writing VEO instantiation template for 'cnt_50m'... Finished executing Tcl generator. Executing Tcl generator... INFO:sim - Writing VHDL behavioral simulation model for 'cnt_50m'... WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this core. Overriding with simulation file type 'Structural'. INFO:sim - Writing Verilog structural simulation model for 'cnt_50m'... Finished executing Tcl generator. Generating ASY schematic symbol... Initializing IP model... Finished initializing IP model. Finished generating ASY schematic symbol. Executing Tcl generator... INFO:sim - Generating SYM schematic symbol for 'cnt_50m'... Finished executing Tcl generator. Generating metadata file... Finished generating metadata file. Generating ISE project... Finished generating ISE project.Generating README file... Creating readme './tmp/_cgcnt_50m_readme.txt'. Finished generating README file. Generating FLIST file... Finished FLIST file generation. Preparing output directory... Finished preparing output directory. Launching README viewer... Launched README viewer. Moving files to output directory... Finished moving files to output directory Wrote file for project 'C:myworkipcore_dircnt_50m.cgp'. Core Generator create command completed successfully. INFO:HDLCompiler:1693 - Analyzing Verilog file "C:/mywork/ipcore_dir/cnt_50m.v" into library work INFO:HDLCompiler:1061 - Parsing VHDL file "C:/mywork/ipcore_dir/cnt_50m.vhd" into library work INFO:ProjectMgmt:659 - Parsing design hierarchy completed successfully.] Good luck ! |
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您是否尝试解决“C： TEMP 中无写入权限”问题？
以上来自于谷歌翻译 以下为原文 Did you try resolving the "No write access in C:TEMP" issue? |
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