双向引脚模块怎么实现

我试图在Spartan 3e启动板上实现一个简单的双向引脚模块。
行为模拟（ISim）工作正常但后期翻译没有。输入而不是跟随双向引脚，在后转换模拟中变为常数1'bx。
合成期间我没有收到任何警告。
码：
`timescale 1ns / 1ps
模块bidir_pin（IN1，PIN，OUT1，OE）;
输出线IN1;
//从模块向FPGA发出信号
输入密码;
//由PIN表示的双向端口
输入OUT1;
//从FPGA发送信号到BusPin模块
输入OE;
//控制信号确定BusPin方向
分配PIN = OE？
OUT1：1'bZ;
分配IN1 = PIN;
// buf i_buf（IN，PIN）;
// bufif1 o_buf（PIN，OUT，OE）;
endmodule
（我已经尝试过这里显示的两种实现;两者都给我同样的问题）
行为（顶部）和翻译后（底部）模拟在这里：
关于翻译后模拟的注意事项，当它应该跟随PIN时，IN1是一个常数1'bx。我已经查看了RTL原理图，据我所知，它看起来是正确的：
我也尝试锁定PIN，然后将其发送到IN1，我也遇到了同样的问题：
任何人都可以弄明白发生了什么？
如果有帮助，这是我的未锁定版本的测试平台。
`timescale 1ns / 1ps
bidir_pin_test模块;
//输入
reg OUT1 = 1;
reg OE;
reg SEL = 1;
reg INPUT = 0;
//输出
电线IN1;
//比迪
线PIN;
//实例化被测单元（UUT）
bidir_pin uut（
.IN1（IN1），
.PIN（PIN），
.OUT1（OUT1），
.OE（OE）
）;
分配PIN = SEL？
输入：1'bz;
最初开始
//初始化输入
OE = 0;
//等待100 ns以完成全局重置
＃100;
#100 SEL = 0;
＃100 OE = 1;
//在这里添加刺激
结束
endmodule
谢谢。
`timescale 1ns / 1psmodule bidir_pin（IN1，PIN，OUT1，OE）;
输出线IN1;
//从模块向FPGA内输出信号;
//由PIN输入OUT1表示的双向端口;
//从FPGA发信号到BusPin模块输入OE;
//控制信号确定BusPin方向分配PIN = OE？
OUT1：1'bZ;
分配IN1 = PIN;
// buf i_buf（IN，PIN）;
// bufif1 o_buf（PIN，OUT，OE）;
endmodule



以下为原文

I am trying to implement a simple bidirectional pin module on the Spartan 3e starter board.

The behavioural simulation (ISim) works fine but the post translate doesn't.The input, instead of following the bidirectional pin, becomes a constant 1'bx in the post translate simulation. I don't get any warnings during synthesis.

Code:
`timescale 1ns / 1psmodule bidir_pin( IN1, PIN, OUT1, OE);  output wire IN1; // signal from module into FPGA  inout  PIN; // bi-directional port represented by PIN  input  OUT1; // signal from FPGA into BusPin module  input OE; // control signal determining BusPin directionassign PIN = OE ? OUT1 : 1'bZ;assign IN1 = PIN ;//buf i_buf ( IN, PIN);   //bufif1 o_buf ( PIN, OUT, OE ); endmodule  (I've tried both implementations shown here; both give me the same problem)

The behavioural (top) and post translate (bottom) simulation are here:



notice for the post-translate simulation, IN1 is a constant 1'bx when it should be following PIN.I've looked at the RTL schematic and as far as I know it looks correct:




I also tried to latch PIN, and then send it to IN1, and I get the same problem:




Can anyone figure out what's going on? Here is my testbench for the un-latched version if that helps.

`timescale 1ns / 1psmodule bidir_pin_test;// Inputsreg OUT1=1;reg OE;reg SEL = 1;reg INPUT = 0;// Outputswire IN1;// Bidirswire PIN;// Instantiate the Unit Under Test (UUT)bidir_pin uut (.IN1(IN1), .PIN(PIN), .OUT1(OUT1), .OE(OE));assign PIN = SEL ? INPUT : 1'bz;initial begin// Initialize InputsOE = 0;// Wait 100 ns for global reset to finish#100;      #100 SEL = 0;#100 OE = 1;// Add stimulus hereend      endmodule Thanks.
`timescale 1ns / 1ps

module bidir_pin( IN1, PIN, OUT1, OE);
      output wire IN1;     // signal from module into FPGA
      inout  PIN;     // bi-directional port represented by PIN
      input  OUT1;     // signal from FPGA into BusPin module
      input     OE;     // control signal determining BusPin direction

   
    assign PIN = OE ? OUT1 : 1'bZ;
    assign IN1 = PIN ;

   
    //buf i_buf ( IN, PIN);     
      //bufif1 o_buf ( PIN, OUT, OE );     
   
endmodule