怎么去设备？

嗨Sridar，
FPGA的基本构建块实际上是SLICE。
实际上，它们是由几个LUT和FF组成的，但我建议查看所有核心使用多少个切片然后将它们加在一起。
你可以添加一个保证金，但实际上，这些工具将能够以一点点性能为代价来共享SLICE ......
最好的祝福，
德赖斯
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以下为原文

Hi Sridar,
 
the basic building blocks of FPGAs are actually SLICEs.
So indeed, they are made out of several LUTs and FFs, but I would recommend to look how many slices all the cores use and then add those together.
 
You could add a margin, but in reality, the tools will be able to share SLICEs at the cost of a little bit of performance...
 
 
Best regards,
Dries
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这里有一些关于切片与LUT的更多信息，您可能会发现它们很有用
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/how-to-find-no-of-slices-utilized-from-the-no-of-slice-registers/m-p/74159
BT



以下为原文

>> FPGA的基本构建块实际上是SLICE。
但是，spartan-3系列每片有2个LUT，而spartan-6每片有4个LUT和6位架构。
所以，它不具有直接可比性，对吧？
FPGA怪胎



以下为原文

>> the basic building blocks of FPGAs are actually SLICEs.
 
But, spartan-3 family has 2 LUT per slice and spartan-6 has 4 LUT per slice and of 6-bit architecture. So, it is not directly comparable, right?
 
FPGA freak

Sridar，
正确。
“等效逻辑单元”试图使其正常化，但也会导致一些潜在的混淆。
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/How-does-Xilinx-come-up-with-number-of-Logic-Cells-for-Spartan-6/td-p/72461
尽管如此，理解底层架构肯定有帮助。
BT



以下为原文

sridar写道：
>> FPGA的基本构建块实际上是SLICE。
但是，spartan-3系列每片有2个LUT，而spartan-6每片有4个LUT和6位架构。
所以，它不具有直接可比性，对吧？
正确。
但是，如果您知道要使用的架构中的IP切片数量（Spartan-3 / Spartan-6），您将获得完整设计的准确估计值。
最好的祝福，
德赖斯
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以下为原文

 

sridar wrote:
>> the basic building blocks of FPGAs are actually SLICEs.
 
But, spartan-3 family has 2 LUT per slice and spartan-6 has 4 LUT per slice and of 6-bit architecture. So, it is not directly comparable, right?
 

 
Correct.
 
However, if you know the amount of slices for your IP in the architecture you're going to use (Spartan-3/Spartan-6), you will get accurate estimates for your complete design.
 
 
Best regards,
Dries
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